CY7C131E_13 Datasheet, PDF (1/20 Pages) Cypress Semiconductor – 1 K / 2 K x 8 Dual-port Static RAM

CY7C131E, CY7C131AE
CY7C136E, CY7C136AE
1 K / 2 K × 8 Dual-port Static RAM
1 K / 2 K × 8 Dual-port Static RAM
Features
■ True dual-ported memory cells, which allow simultaneous
reads of the same memory location
■ 1 K / 2 K × 8 organization
■ 0.35 micron complementary metal oxide semiconductor
(CMOS) for optimum speed and power
■ High speed access: 15 ns
■ Low operating power: I_CC = 110 mA (typical),
Standby: I_SB3 = 0.05 mA (typical)
■ Fully asynchronous operation
■ Automatic power-down
■ BUSY output flag to indicate access to the same location by
both ports
■ INT flag for port-to-port communication
■ Available in 52-pin plastic leaded chip carrier (PLCC), 52-pin
plastic quad flat package (PQFP)
■ Pb-free packages available
Functional Description
CY7C131E / CY7C131AE / CY7C136E / CY7C136AE are
high-speed, low-power CMOS 1 K / 2 K × 8 dual-port static
RAMs. Two ports are provided permitting independent access to
any location in memory. The CY7C131E / CY7C131AE /
CY7C136E / CY7C136AE can be used as a standalone dual-port
static RAM. It is the solution to applications requiring shared or
buffered data, such as cache memory for DSP, bit-slice, or multi-
processor designs.
Each port has independent control pins; chip enable (CE), write
enable (R/W), and output enable (OE). Two flags are provided
on each port, BUSY and INT. The BUSY flag signals that the port
is trying to access the same location, which is currently being
accessed by the other port. The INT is an interrupt flag indicating
that data is placed in a unique location^[1]. The BUSY and INT
flags are push pull outputs. An automatic power-down feature is
controlled independently on each port by the chip enable (CE)
pins.
The CY7C131E / CY7C131AE / CY7C136E / CY7C136AE are
available in 52-pin Pb-free PLCC and 52-pin Pb-free PQFP.
Logic Block Diagram
R/W_L
CE_L
OE_L
I/O_7L
I/O_0L
BUSY_L^[2]
A _9/10L
[4]
A _0L
I/O
CONTROL
I/O
CONTROL
ADDR
DECODER
MEMORY
ARRAY
ADDR
DECODER
[3]
INT_L
CE_L
OE_L
R/W_L
77CC_A11_R331_B6LEE_IOT//77_RGCC_AI1_C1T33_I1_O6AANEE/
A(7RCB1IT3R0/A7TCI1O3N1 LOONGLIYC)
AND
IN^INT^TE^ER^RR^RU^UP^PT^TL^LO^OG^GI^IC^C
CE_R
OE_R
R/W_R
R/W_R
CE_R
OE_R
I/O_7R
I/O_0R
BUSY_R^[2]
A _9/10R
[4]
A _0R
INT_R^[3]
Notes
1. Unique location used by interrupt flag: 1 K × 8: Left port reads from 3FE, Right port reads from 3FF; 2 K × 8: Left port reads from 7FE, Right port reads from 7FF.
2. BUSY is a push-pull output. No pull-up resistor required.
3. INT: push-pull output. No pull-up resistor required.
4. 1 K × 8: A0–A9, 2 K × 8: A0–A10, address lines are for both left and right ports.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-64231 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 15, 2013