CY7C1318CV18_11 Datasheet, PDF (1/29 Pages) Cypress Semiconductor – 18-Mbit DDR II SRAM 2-Word Burst Architecture

CY7C1318CV18, CY7C1320CV18
18-Mbit DDR II SRAM 2-Word
Burst Architecture
18-Mbit DDR II SRAM 2-Word Burst Architecture
Features
■ 18-Mbit density (1 M × 18, 512 K × 36)
■ 267-MHz clock for high bandwidth
■ 2-word burst for reducing address bus frequency
■ Double data rate (DDR) interfaces
(data transferred at 534 MHz) at 267 MHz
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■ Synchronous internally self-timed writes
■ DDR II operates with 1.5 cycle read latency when delay lock
loop (DLL) is enabled
■ Operates similar to a DDR I device with one cycle read latency
in DLL Off mode
■ 1.8 V core power supply with high-speed transceiver logic
(HSTL) inputs and outputs
■ Variable drive HSTL output buffers
■ Expanded HSTL output voltage (1.4 V – V_DD)
■ Available in 165-ball fine pitch ball grid array (FPBGA) package
(13 × 15 × 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ JTAG 1149.1 compatible test access port
■ DLL for accurate data placement
Configurations
CY7C1318CV18 – 1M × 18
CY7C1320CV18 – 512K × 36
Functional Description
The CY7C1318CV18, and CY7C1320CV18 are 1.8 V
synchronous pipelined SRAMs equipped with DDR II
architecture. The DDR II consists of an SRAM core with
advanced synchronous peripheral circuitry and a one-bit burst
counter. Addresses for read and write are latched on alternate
rising edges of the input (K) clock. Write data is registered on the
rising edges of both K and K. Read data is driven on the rising
edges of C and C if provided, or on the rising edge of K and K if
C/C are not provided. For CY7C1318CV18 and
CY7C1320CV18, the burst counter takes in the least significant
bit of the external address and bursts two 18-bit words (in the
case of CY7C1318CV18) of two 36-bit words (in the case of
CY7C1320CV18) sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs, D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need to capture data
separately from each individual DDR SRAM in the system
design. Output data clocks (C/C) enable maximum system
clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-07160 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised February 2, 2011
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