CY7C1317KV18 Datasheet, PDF (1/33 Pages) Cypress Semiconductor – 18-Mbit DDR II SRAM Four-Word Burst Architecture

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CY7C1317KV18, CY7C1917KV18
CY7C1319KV18, CY7C1321KV18
18-Mbit DDR II SRAM
Four-Word Burst Architecture
18-Mbit DDR II SRAM Four-Word Burst Architecture
Features
■ 18 Mbit density (2 M × 8, 2 M × 9, 1 M × 18, 512 K × 36)
■ 333-MHz clock for high bandwidth
■ Four-word burst for reducing address bus frequency
■ Double data rate (DDR) interfaces 
(data transferred at 666 MHz) at 333 MHz
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■ Synchronous internally self-timed writes
■ DDR II operates with 1.5 cycle read latency when DOFF is
asserted HIGH
■ Operates similar to DDR I device with one cycle read latency
when DOFF is asserted LOW
■ 1.8 V core power supply with HSTL inputs and outputs
■ Variable drive HSTL output buffers
■ Expanded HSTL output voltage (1.4 V–V_DD)
❐ Supports both 1.5 V and 1.8 V I/O supply
■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ JTAG 1149.1 compatible test access port
■ Phase locked loop (PLL) for accurate data placement
Configurations
CY7C1317KV18 – 2 M × 8
CY7C1917KV18 – 2 M × 9
CY7C1319KV18 – 1 M × 18
CY7C1321KV18 – 512 K × 36
Functional Description
The CY7C1317KV18, CY7C1917KV18, CY7C1319KV18, and
CY7C1321KV18 are 1.8 V Synchronous Pipelined SRAMs
equipped with DDR II architecture. The DDR II consists of an
SRAM core with advanced synchronous peripheral circuitry and
a two-bit burst counter. Addresses for read and write are latched
on alternate rising edges of the input (K) clock. Write data is
registered on the rising edges of both K and K. Read data is
driven on the rising edges of C and C if provided, or on the rising
edge of K and K if C/C are not provided. Each address location
is associated with four 8-bit words in the case of CY7C1317KV18
and four 9-bit words in the case of CY7C1917KV18 that burst
sequentially into or out of the device. The burst counter always
starts with a ‘00’ internally in the case of CY7C1317KV18 and
CY7C1917KV18. For CY7C1319KV18 and CY7C1321KV18,
the burst counter takes in the least two significant bits of the
external address and bursts four 18-bit words in the case of
CY7C1319KV18, and four 36-bit words in the case of
CY7C1321KV18, sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs, D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need to capture data
separately from each individual DDR SRAM in the system
design. Output data clocks (C/C) enable maximum system
clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Selection Guide
Description
Maximum operating frequency
Maximum operating current
333 MHz
300
×8
370
×9
370
×18
370
×36
440
300 MHz
300
350
350
350
420
250 MHz
250
320
320
320
370
200 MHz
200
280
280
290
330
167 MHz
167
260
260
270
300
Unit
MHz
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-58906 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised February 28, 2011
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