CY7C1313CV18_11 Datasheet, PDF (1/29 Pages) Cypress Semiconductor – 18-Mbit QDR® II SRAM 4-Word Burst Architecture

CY7C1313CV18
CY7C1315CV18
18-Mbit QDR^® II SRAM 4-Word
Burst Architecture
18-Mbit QDR® II SRAM 4-Word Burst Architecture
Features
Configurations
■ Separate independent read and write data ports
❐ Supports concurrent transactions
■ 300 MHz clock for high bandwidth
■ 4-word burst for reducing address bus frequency
■ Double Data Rate (DDR) interfaces on both read and write ports
(data transferred at 600 MHz) at 300 MHz
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■ Single multiplexed address input bus latches address inputs
for both read and write ports
■ Separate port selects for depth expansion
■ Synchronous internally self-timed writes
■ QDR^® II operates with 1.5 cycle read latency when the Delay
Lock Loop (DLL) is enabled
■ Operates as a QDR I device with 1 cycle read latency in DLL
off mode
■ Available in x 18, and x 36 configurations
■ Full data coherency, providing most current data
■ Core V_DD = 1.8 (±0.1V); I/O V_DDQ = 1.4V to V_DD
■ Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ Variable drive HSTL output buffers
■ JTAG 1149.1 compatible test access port
■ Delay Lock Loop (DLL) for accurate data placement
CY7C1313CV18 – 1M x 18
CY7C1315CV18 – 512K x 36
Functional Description
The CY7C1313CV18, and CY7C1315CV18 are 1.8V
Synchronous Pipelined SRAMs, equipped with QDR^® II archi-
tecture. QDR II architecture consists of two separate ports: the
read port and the write port to access the memory array. The
read port has dedicated data outputs to support read operations
and the write port has dedicated data inputs to support write
operations. QDR II architecture has separate data inputs and
data outputs to completely eliminate the need to “turnaround” the
data bus required with common I/O devices. Access to each port
is accomplished through a common address bus. Addresses for
read and write addresses are latched on alternate rising edges
of the input (K) clock. Accesses to the QDR II read and write
ports are completely independent of one another. In order to
maximize data throughput, both read and write ports are
provided with DDR interfaces. Each address location is
associated with four 18-bit words (CY7C1313CV18) or 36-bit
words (CY7C1315CV18) that burst sequentially into or out of the
device. Because data can be transferred into and out of the
device on every rising edge of both input clocks (K and K and C
and C), memory bandwidth is maximized while simplifying
system design by eliminating bus “turnarounds”.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
300 MHz
300
x18
840
x36
985
278 MHz
278
760
910
250 MHz
250
705
830
200 MHz
200
590
675
167 MHz
167
505
570
Unit
MHz
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-07165 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised February 02, 2011
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