CY7C130_05 Datasheet, PDF (1/19 Pages) Cypress Semiconductor – 1K x 8 Dual-Port Static RAM

CY7C130/CY7C131
CY7C140/CY7C141
Features
• True Dual-Ported memory cells which allow simulta-
neous reads of the same memory location
• 1K x 8 organization
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 15 ns
• Low operating power: I_CC = 110 mA (max.)
• Fully asynchronous operation
• Automatic power-down
• Master CY7C130/CY7C131 easily expands data bus
width to 16 or more bits using slave CY7C140/CY7C141
• BUSY output flag on CY7C130/CY7C131; BUSY input
on CY7C140/CY7C141
• INT flag for port-to-port communication
• Available in 48-pin DIP (CY7C130/140), 52-pin PLCC,
52-Pin TQFP.
• Pb-Free packages available
1K x 8 Dual-Port Static RAM
Functional Description
The CY7C130/CY7C131/CY7C140 and CY7C141 are
high-speed CMOS 1K by 8 dual-port static RAMs. Two ports
are provided permitting independent access to any location in
memory. The CY7C130/ CY7C131 can be utilized as either a
standalone 8-bit dual-port static RAM or as a master dual-port
RAM in conjunction with the CY7C140/CY7C141 slave
dual-port device in systems requiring 16-bit or greater word
widths. It is the solution to applications requiring shared or
buffered data, such as cache memory for DSP, bit-slice, or
multiprocessor designs.
Each port has independent control pins; chip enable (CE),
write enable (R/W), and output enable (OE). Two flags are
provided on each port, BUSY and INT. BUSY signals that the
port is trying to access the same location currently being
accessed by the other port. INT is an interrupt flag indicating
that data has been placed in a unique location (3FF for the left
port and 3FE for the right port). An automatic power-down
feature is controlled independently on each port by the chip
enable (CE) pins.
The CY7C130 and CY7C140 are available in 48-pin DIP. The
CY7C131 and CY7C141 are available in 52-pin PLCC, 52-pin
Pb-free PLCC, 52-pin PQFP and 52-pin Pb-free PQFP.
Logic Block Diagram
Pin Configurations
R/W_L
CE_L
OE_L
I/O_7L
I/O_0L
BUSY_L^[1]
A _9L
A _0L
[2]
INT_L
I/O
CONTROL
I/O
CONTROL
ADDRESS
DECODER
MEMORY
ARRAY
ADDRESS
DECODER
CE_L
OE_L
R/W_L
ARBITRATION
LOGIC
(7C130/7C131 ONLY)
AND
INTERRUPT LOGIC
CE_R
OE_R
R/W_R
R/W_R
CE_R
OE_R
I/O_7R
I/O_0R
BUSY_R
A _9R
A _0R
INT_R^[2]
DIP
Top View
CE _L
R/W _L
BUSY _L
INT_L
OE_L
A_0L
A_1L
A_2L
A_3L
A_4L
A_5L
A_6L
A_7L
A_8L
A_9L
I/O_0L
I/O_1L
I/O_2L
I/O_3L
I/O_4L
I/O_5L
I/O_6L
I/O_7L
GND
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12 _7C130 37
13 7C140 36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
V_CC
CE_R
R/W_R
BUSY_R
INT_R
OE_R
A_0R
A_1R
A_2R
A_3R
A_4R
A_5R
A_6R
A_7R
A_8R
A_9R
I/O_7R
I/O_6R
I/O_5R
I/O_4R
I/O_3R
I/O_2R
I/O_1R
I/O_0R
Note:
1. CY7C130/CY7C131 (Master): BUSY is open drain output and requires pull-up resistor
CY7C140/CY7C141 (Slave): BUSY is input.
2. Open drain outputs: pull-up resistor required.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-06002 Rev. *D
Revised August 29, 2005