CY7C1303CV25 Datasheet, PDF (1/21 Pages) Cypress Semiconductor – 18-Mbit Burst of 2 Pipelined SRAM with QDR Architecture

PRELIMINARY
CY7C1303CV25
CY7C1306CV25
18-Mbit Burst of 2 Pipelined SRAM with
QDR™ Architecture
Features
■ Separate independent read and write data ports
❐ Supports concurrent transactions
■ 167 MHz clock for high bandwidth
❐ 2.5 ns Clock-to-Valid access time
■ 2-word burst on all accesses
■ Double Data Rate (DDR) interfaces on both read and write ports
(data transferred at 333 MHz) at 167 MHz
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
■ Single multiplexed address input bus latches address inputs
for both read and write ports
■ Separate port selects for depth expansion
■ Synchronous internally self-timed writes
■ 2.5V core power supply with HSTL inputs and outputs
■ Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)
■ Variable drive HSTL output buffers
■ Expanded HSTL output voltage (1.4V–1.9V)
■ JTAG interface
■ Variable Impedance HSTL
Configurations
CY7C1303CV25 – 1M x 18
CY7C1306CV25 – 512K x 36
Functional Description
The CY7C1303CV25 and CY7C1306CV25 are 2.5V
Synchronous Pipelined SRAMs, equipped with QDR™
architecture. QDR architecture consists of two separate ports:
the read port and the write port to access the memory array. The
read port has data outputs to support read operations and the
write port has data inputs to support write operations. QDR
architecture has separate data inputs and data outputs to
completely eliminate the need to “turn-around” the data bus
required with common I/O devices. Access to each port is
accomplished through a common address bus. The read
address is latched on the rising edge of the K clock and the write
address is latched on the rising edge of the K clock. Accesses to
the QDR read and write ports are completely independent of one
another. All accesses are initiated synchronously on the rising
edge of the positive input clock (K). To maximize data
throughput, both read and write ports are provided with DDR
interfaces. Therefore, data can be transferred into the device on
every rising edge of both input clocks (K and K) and out of the
device on every rising edge of the output clock (C and C, or K
and K when in single clock mode) thereby maximizing
performance while simplifying system design. Each address
location is associated with two 18-bit words (CY7C1303CV25),
or 36-bit words (CY7C1306CV25) that burst sequentially into or
out of the device.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K/K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Selection Guide
Maximum Operating Frequency
Maximum Operating Current
Description
167 MHz
167
500
Unit
MHz
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-44701 Rev. *B
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 31, 2009
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