CY7C1302DV25_11 Datasheet, PDF (1/25 Pages) Cypress Semiconductor – 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture JTAG Interface

CY7C1302DV25
9-Mbit Burst of Two Pipelined SRAMs
with QDR™ Architecture
9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture
Features
■ Separate independent Read and Write data ports
❐ Supports concurrent transactions
■ 167-MHz clock for high bandwidth
❐ 2.5 ns Clock-to-Valid access time
■ 2-word burst on all accesses
■ Double Data Rate (DDR) interfaces on both Read and Write
ports (data transferred at 333 MHz) @ 167 MHz
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Two input clocks for output data (C and C) to minimize
clock-skew and flight-time mismatches.
■ Single multiplexed address input bus latches address inputs
for both Read and Write ports
■ Separate Port Selects for depth expansion
■ Synchronous internally self-timed writes
■ 2.5 V core power supply with HSTL Inputs and Outputs
■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
■ Variable drive HSTL output buffers
■ Expanded HSTL output voltage (1.4 V–1.9 V)
■ JTAG Interface
Configurations
CY7C1302DV25 – 512 K × 18
Functional Description
The CY7C1302DV25 is a 2.5 V Synchronous Pipelined SRAM
equipped with QDR™ architecture. QDR architecture consists of
two separate ports to access the memory array. The Read port
has dedicated data outputs to support Read operations and the
Write Port has dedicated data inputs to support Write operations.
Access to each port is accomplished through a common address
bus. The Read address is latched on the rising edge of the
K clock and the Write address is latched on the rising edge of
K clock. QDR has separate data inputs and data outputs to
completely eliminate the need to “turn-around” the data bus
required with common I/O devices. Accesses to the
CY7C1302DV25 Read and Write ports are completely
independent of one another. All accesses are initiated
synchronously on the rising edge of the positive input clock (K).
In order to maximize data throughput, both Read and Write ports
are equipped with DDR interfaces. Therefore, data can be
transferred into the device on every rising edge of both input
clocks (K and K) and out of the device on every rising edge of
the output clock (C and C, or K and K in a single clock domain)
thereby maximizing performance while simplifying system
design. Each address location is associated with two 18-bit
words that burst sequentially into or out of the device.
Depth expansion is accomplished with a Port Select input for
each port. Each Port Select allows each port to operate
independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05625 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 9, 2011
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