CY7C1300A Datasheet, PDF (1/12 Pages) Cypress Semiconductor – 128K X 36 Dual I/O Dual Address Synchronous SRAM

CY7C1300A
128K X 36 Dual I/O Dual Address Synchronous SRAM
Features
• Fast clock speed: 100 and 83 MHz
• Fast access times: 5.0/6.0 ns max.
• Single clock operation
• Single 3.3V –5% and +5% power supply V_CC
• Separate V_CCQ for output buffer
• Two chip enables for simple depth expansion
• Address, data input, CE1X, CE2X, CE1Y, CE2Y, PTX,
PTY, WEX, WEY, and data output registers on-chip
• Concurrent Reads and Writes
• Two bidirectional data buses
• Can be configured as separate I/O
• Pass-through feature
• Asynchronous output enables (OEX, OEY)
• LVTTL-compatible I/O
• Self-timed Write
• Automatic power-down
• 176-pin TQFP package
Functional Description
The CY7C1300A SRAM integrates 131,072 × 36 SRAM cells
with advanced synchronous peripheral circuitry. It employs
high-speed, low-power CMOS designs using advanced
triple-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high-valued
resistors.
Logic Block Diagram^[1]
The CY7C1300A allows the user to concurrently perform
Reads, Writes, or pass-through cycles in combination on the
two data ports. The two address ports (AX, AY) determine the
Read or Write locations for their respective data ports (DQX,
DQY).
All input pins except output enable pins (OEX, OEY) are gated
by registers controlled by a positive-edge-triggered clock
(CLK) input. The synchronous inputs include all addresses,
data inputs, depth-expansion chip enables (CE1X, CE2X,
CE1Y and CE2Y), pass-through controls (PTX and PTY), and
Read–Write control (WEX and WEY).
The pass-through feature allows data to be passed from one
port to another, in either direction. The PTX input must be
asserted to pass data from port X to port Y. The PTY will
likewise pass data from port Y to port X. A pass-through
operation takes precedence over a Read operation.
When AX and AY are the same, certain protocols are followed.
If both ports are Read, the reads occur normally. If one port is
written and the other is read, the read from the array will occur
before the data is written. If both ports are written, only the data
on DQY will be written to the array.
The CY7C1300A operates from a +3.3V power supply. All
inputs and outputs are LVTTL-compatible. These dual I/O,
dual address synchronous SRAMs are well suited for ATM,
Ethernet switches, routers, cell/frame buffers, SNA switches,
and shared memory applications.
The CY7C1300A needs one extra cycle after power for proper
power-on reset. The extra cycle is needed after V_CC is stable
on the device.
This device is available in a 176-pin TQFP package.
Y
Note:
1. For 128K x 36 devices, AX and AY are 17-bit-wide buses.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05075 Rev. *C
Revised January 19, 2003