CY7C1298A Datasheet, PDF (1/12 Pages) Cypress Semiconductor – 64K x 18 Synchronous Burst RAM Pipelined Output

298A
CY7C1298A/
GVT7164C18
64K x 18 Synchronous Burst RAM
Pipelined Output
Features
• Fast access times: 5, 6, 7, and 8 ns
• Fast clock speed: 100, 83, 66, and 50 MHz
• Provide high-performance 3-1-1-1 access rate
• Fast OE access times: 5 and 6 ns
• Optimal for performance (two cycle chip deselect,
depth expansion without wait state)
• Single +3.3V –5 to +10% power supply
• 5V tolerant inputs except I/Os
• Clamp diodes to V_SSQ at all inputs and outputs
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
• Three chip enables for depth expansion and address
pipeline
• Address, control, input, and output pipeline registers
• Internally self-timed Write Cycle
• Write pass-through capability
• Burst control pins (interleaved or linear burst se-
quence)
• Automatic power-down for portable applications
• High-density, high-speed packages
• Low capacitive bus loading
• High 30-pF output drive capability at rated access time
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low-power CMOS designs using advanced dou-
ble-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high valued
resistors.
The CY7C1298A/GVT7164C18 SRAM integrates 65536x18
SRAM cells with advanced synchronous peripheral circuitry
and a 2-bit counter for internal burst operation. All synchro-
nous inputs are gated by registers controlled by a posi-
tive-edge-triggered Clock input (CLK). The synchronous in-
puts include all addresses, all data inputs, address-pipelining
Chip Enable (CE), depth-expansion Chip Enables (CE2 and
CE2), burst control inputs (ADSC, ADSP, and ADV), Write En-
ables (WEL, WEH, and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and
Burst Mode Control (MODE). The data outputs (Q), enabled
by OE, are also asynchronous.
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address Status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the burst advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed Write cycle. Write cycles can be one to
four bytes wide as controlled by the write control inputs. Indi-
vidual byte write allows individual byte to be written. WEL con-
trols DQ1–DQ8 and DQP1. WEH controls DQ9–DQ16 and
DQP2. WEL and WEH can be active only with BWE being
LOW. GW being LOW causes all bytes to be written. This de-
vice also incorporates Write pass-through capability and pipe-
lined enable circuit for better system performance.
The CY7C1298A/GVT7164C18 operates from a +3.3V power
supply. All inputs and outputs are TTL-compatible. The device
is ideally suited for 486, Pentium®, 680x0, and PowerPC™
systems and for systems that are benefited from a wide syn-
chronous data bus.
Selection Guide
7C1298A-100
7164C18-5
Maximum Access Time (ns)
5
Maximum Operating Current (mA)
360
Maximum CMOS Standby Current (mA)
2
Pentium is a registered trademark of Intel Corporation.
PowerPC is a trademark of International Business Machines, Inc.
7C1298A-83
7164C18-6
6
315
2
7C1298A-66
7164C18-7
7
270
2
7C1298A-50
7164C18-8
8
225
2
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05194 Rev. *A
Revised January 19, 2003