CY7C128A_06 Datasheet, PDF (1/9 Pages) Cypress Semiconductor – 2K x 8 Static RAM

CY7C128A
2K x 8 Static RAM
Features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• High speed
— 15 ns
• Low active power
— 660 mW (commercial)
• Low standby power
— 110 mW (20 ns)
• TTL-compatible inputs and outputs
• Capable of withstanding greater than 2001V electro-
static discharge
• Available in Pb-free and non Pb-free 24-pin Molded
SOJ, non Pb-free 24-pin (300-Mil) Molded DIP
Logic Block Diagram
A₁₀
A₉
A₈
A₇
A₆
A₅
A₄
CE
WE
OE
INPUT BUFFER
128 x 16 x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
A₃ A₂ A₁ A₀
Functional Description
The CY7C128A is a high-performance CMOS static RAM
organized as 2048 words by 8 bits. Easy memory expansion
is provided by an active LOW Chip Enable (CE), and active
LOW Output Enable (OE) and tri-state drivers. The CY7C128A
has an automatic power-down feature, reducing the power
consumption by 83% when deselected.
Writing to the device is accomplished when the Chip Enable
(CE) and Write Enable (WE) inputs are both LOW.
Data on the eight I/O pins (I/O₀ through I/O₇) is written into the
memory location specified on the address pins (A₀ through
A₁₀).
Reading the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while Write Enable (WE)
remains HIGH. Under these conditions, the contents of the
memory location specified on the address pins will appear on
the eight I/O pins.
The I/O pins remain in high-impedance state when Chip
Enable (CE) or Output Enable (OE) is HIGH or Write Enable
(WE) is LOW.
The CY7C128A utilizes a die coat to insure alpha immunity.
Pin Configurations
DIP/SOJ
Top View
A₇ 1
24 VCC
A₆ 2
A_{5 3}
A_{4 4}
23 A₈
22 A₉
21 WE
A_{3 5}
20 OE
I/O₀
A₂
A₁
6
19
7 ^7C128A18
A₁₀
CE
I/O₁
A₀ 8
17 I/O₇
I/O₂
I/O₀ 9
I/O₁ 10
16 ^I/O6
15 ^I/O5
I/O₃
I/O₂ 11
GND 12
14 ^I/O4
13 I/O₃
I/O₄
I/O₅
C128A–2
I/O₆
I/O₇
C128A–1
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05028 Rev. *A
Revised August 3, 2006