CY7C128A Datasheet, PDF (1/9 Pages) Cypress Semiconductor – 2K x 8 Static RAM

1CY 7C12 8A
CY7C128A
Features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• High speed
— 15 ns
• Low active power
— 440 mW (commercial)
— 550 mW (military)
• Low standby power
— 110 mW
• TTL-compatible inputs and outputs
• Capable of withstanding greater than 2001V electro-
static discharge
• V_IH of 2.2V
2K x 8 Static RAM
Functional Description
The CY7C128A is a high-performance CMOS static RAM or-
ganized as 2048 words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE), and active LOW
output enable (OE) and three-state drivers. The CY7C128A
has an automatic power-down feature, reducing the power
consumption by 83% when deselected.
Writing to the device is accomplished when the chip enable
(CE) and write enable (WE) inputs are both LOW.
Data on the eight I/O pins (I/O₀ through I/O₇) is written into the
memory location specified on the address pins (A₀ through
A₁₀).
Reading the device is accomplished by taking chip enable
(CE) and output enable (OE) LOW while write enable (WE) remains
HIGH. Under these conditions, the contents of the memory location
specified on the address pins will appear on the eight I/O pins.
The I/O pins remain in high-impedance state when chip enable
(CE) or output enable (OE) is HIGH or write enable (WE) is LOW.
The CY7C128A utilizes a die coat to insure alpha immunity.
Logic Block Diagram
A₁₀
A₉
A₈
A₇
A₆
A₅
A₄
CE
WE
OE
INPUT BUFFER
128 x 16 x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
A₃ A₂ A₁ A₀
Selection Guide
Maximum Access Time (ns)
Maximum Operating
Current (mA)
Commercial
Military
Maximum Standby
Current (mA)
Commercial
Military
I/O₀
I/O₁
I/O₂
I/O₃
I/O₄
I/O₅
I/O₆
I/O₇
C128A–1
Pin Configurations
DIP/SOJ
Top View
A₇ 1
24 VCC
A₆ 2
A₅ 3
A_{4 4}
23 A8
22 A9
21 WE
A_{3 5}
20 OE
A₂
A₁
6
19
7 ^7C128A18
A₁₀
CE
A₀ 8
I/O₀ 9
I/O₁ 10
I/O₂ 11
GND 12
17 I/O7
16 ^I/O6
15 ^I/O5
14 ^I/O4
13 I/O3
LCC
Top View
C128A–2
3 2 1 24 23
A₄ 4
22 A₉
A₃ 5
A₂ 6
21 WE
20 OE
A₁ 7 7C128A 19 A₁₀
A₀ 8
18 _CE
I/O₀ 9
17 _I/O7
I/O₁ 10
16 _I/O6
11 12 13 14 15
C128A–3
7C128A–15
15
120
40/40
7C128A–20
20
100
125
40/20
40/20
7C128A–25
25
100
125
20
40
7C128A–35
35
100
100
20
20
7C128A–45
45
100
20
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
December 1988 – Revised December 1992