CY7C12661KV18 Datasheet, PDF (1/30 Pages) Cypress Semiconductor – 36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)

CY7C12661KV18, CY7C12771KV18
CY7C12681KV18, CY7C12701KV18
36-Mbit DDR II+ SRAM 2-Word Burst
Architecture (2.5 Cycle Read Latency)
36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
Features
■ 36-Mbit density (4 M × 8, 4 M × 9, 2 M × 18, 1 M × 36)
■ 550 MHz clock for high bandwidth
■ 2-word burst for reducing address bus frequency
■ Double data rate (DDR) interfaces
(data transferred at 1100 MHz) at 550 MHz
■ Available in 2.5 clock cycle latency
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■ Data valid pin (QVLD) to indicate valid data on the output
■ Synchronous internally self-timed writes
■ DDR II+ operates with 2.5 cycle read latency when DOFF is
asserted HIGH
■ Operates similar to DDR I device with 1 Cycle Read Latency
when DOFF is asserted LOW
■ Core V_DD = 1.8 V ± 0.1 V; I/O V_DDQ = 1.4 V to V_DD[1]
❐ Supports both 1.5 V and 1.8 V I/O supply
■ HSTL inputs and variable drive HSTL output buffers
■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
■ Offered in both Pb-free and non Pb-free Packages
■ JTAG 1149.1 compatible test access port
■ Phase locked loop (PLL) for accurate data placement
Configurations
With Read Cycle Latency of 2.5 cycles:
CY7C12661KV18 – 4 M × 8
CY7C12771KV18 – 4 M × 9
CY7C12681KV18 – 2 M × 18
CY7C12701KV18 – 1 M × 36
Functional Description
The CY7C12661KV18, CY7C12771KV18, CY7C12681KV18,
and CY7C12701KV18 are 1.8 V synchronous pipelined SRAMs
equipped with DDR II+ architecture. The DDR II+ consists of an
SRAM core with advanced synchronous peripheral circuitry.
Addresses for read and write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the rising
edges of both K and K. Read data is driven on the rising edges
of K and K. Each address location is associated with two 8-bit
words (CY7C12661KV18), 9-bit words (CY7C12771KV18),
18-bit words (CY7C12681KV18), or 36-bit words
(CY7C12701KV18) that burst sequentially into or out of the
device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
These devices are down bonded from the 65 nm 72 M
QDRII+/DDRII+ devices and hence have the same I_DD/I_SB1
values and the same JTAG ID code as the equivalent 72 M
device options. For details refer to the application note AN53189,
65 nm Technology InterimQDRII+/DDRII+ SRAM device family
description.
Table 1. Selection Guide
Description
550
MHz
Max operating frequency
550
Max operating current × 8 740
× 9 740
× 18 760
× 36 970
500
MHz
500
690
690
700
890
450
MHz
450
630
630
650
820
400
MHz
400
580
580
590
750
Unit
MHz
mA
Note
1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V_DDQ = 1.4 V to V_DD.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-53195 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised February 2, 2011
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