CY7C1212H Datasheet, PDF (1/15 Pages) Cypress Semiconductor – 1-Mbit (64K x 18) Pipelined Sync SRAM

CY7C1212H
1-Mbit (64K x 18) Pipelined Sync SRAM
Features
• Registered inputs and outputs for pipelined operation
• 64K × 18 common I/O architecture
• 3.3V core power supply (V_DD)
• 2.5V/3.3V I/O power supply (V_DDQ)
• Fast clock-to-output times
— 3.5 ns (for 166-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel^®
Pentium^® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Available in JEDEC-standard lead-free 100-Pin TQFP
package
• “ZZ” Sleep Mode Option
Functional Description^[1]
The CY7C1212H SRAM integrates 64K x 18 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE₁), depth-expansion Chip Enables (CE₂ and CE₃), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW_[A:B], and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two bytes wide as
controlled by the Byte Write control inputs. GW when active
LOW causes all bytes to be written.
The CY7C1212H operates from a +3.3V core power supply
while all outputs may operate either with a +2.5V or +3.3V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Logic Block Diagram
A0, A1, A
ADDRESS
REGISTER
MODE
ADV
CLK
ADSC
ADSP
2 ^A[1:0]
BURST ^Q1
COUNTER
AND
CLR ^LOGIC Q0
DQB,DQPB
BWB
WRITE REGISTER
DQA,DQPA
BWA
WRITE REGISTER
BWE
GW
CE1
CE2
ENABLE
REGISTER
PIPELINED
ENABLE
CE3
OE
DQB,DQPB
WRITE DRIVER
DQA,DQPA
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQPA
DQPB
INPUT
REGISTERS
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05668 Rev. *B
Revised July 6, 2006