CY7C109B_06 Datasheet, PDF (1/10 Pages) Cypress Semiconductor – 128K x 8 Static RAM

CY7C109B
CY7C1009B
Features
• High speed
— t_AA = 12 ns
• Low active power
— 495 mW (max.)
• Low CMOS standby power
— 11 mW (max.) (L Version)
• 2.0V Data Retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE₁, CE₂, and OE options
• CY7C109B is available in standard 400-mil-wide SOJ
and 32-pin TSOP type I packages. The CY7C1009B is
available in a 300-mil-wide SOJ package
128K x 8 Static RAM
Functional Description^[1]
The CY7C109B/CY7C1009B is a high-performance CMOS
static RAM organized as 131,072 words by 8 bits. Easy
memory expansion is provided by an active LOW Chip Enable
(CE₁), an active HIGH Chip Enable (CE₂), an active LOW
Output Enable (OE), and tri-state drivers. Writing to the device
is accomplished by taking Chip Enable One (CE₁) and Write
Enable (WE) inputs LOW and Chip Enable Two (CE₂) input
HIGH. Data on the eight I/O pins (I/O₀ through I/O₇) is then
written into the location specified on the address pins (A₀
through A₁₆).
Reading from the device is accomplished by taking Chip
Enable One (CE₁) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable Two (CE₂) HIGH. Under
these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O₀ through I/O₇) are placed in a
high-impedance state when the device is deselected (CE₁
HIGH or CE₂ LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE₁ LOW, CE₂ HIGH, and WE LOW).
CY7C109B is available in standard 400-mil-wide SOJ and 32-
pin TSOP type I packages. The CY7C1009B is available in a
300-mil-wide SOJ package. The CY7C109B and CY7C1009B
are functionally equivalent in all other respects
Logic Block Diagram
A₀
A₁
A₂
A₃
A₄
A₅
A₆
A₇
A₈
CE₁
CE₂
WE
OE
INPUT BUFFER
128K x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
I/O₀
I/O₁
I/O₂
I/O₃
A₁₁
1
A₉
2
I/O₄ A₈
3
A₁₃
4
I/O₅
WE
CE₂
5
6
A₁₅
7
I/O₆
V_CC
NC
8
9
A₁₆
10
I/O₇
A₁₄
A₁₂
11
12
A₇
13
A₆
14
A₅
15
A₄
16
Pin Configurations^[2]
SOJ
Top View
NC 1
A_{16 2}
A₁₄ 3
A₁₂ 4
A7 5
A6 6
A5 ₇
A4 8
A3 9
A2 10
A1 ₁₁
A0 12
I/O_{0 13}
I/O_{1 14}
I/O_{2 15}
GND ₁₆
32 VCC
31 A₁₅
30 CE₂
29 WE
28 _A13
27 _A8
26 _A9
25 _A11
24 _OE
23 A₁₀
22 CE₁
21 I/O7
20 ^I/O6
19 ^I/O5
18 ^I/O4
17 I/O3
32
31
30
29
28
27
TSOP I
26
Top View
25
(not to scale)
24
23
22
21
20
19
18
17
OE
A₁₀
CE
I/O₇
I/O₆
I/O₅
I/O₄
I/O₃
GND
I/O₂
I/O₁
I/O₀
A₀
A₁
A₂
A₃
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
2. NC pins are not connected on the die.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05038 Rev. *C
Revised August 3, 2006
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