CY7C109BN Datasheet, PDF (1/9 Pages) Cypress Semiconductor – 128K x 8 Static RAM

CY7C109BN
CY7C1009BN
128K x 8 Static RAM
Features
• High speed
— t_AA = 12 ns
• Low active power
— 495 mW (max. 12 ns)
• Low CMOS standby power
— 55 mW (max.) 4 mW
• 2.0V Data Retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE₁, CE₂, and OE options
Functional Description^[1]
The CY7C109BN/CY7C1009BN is a high-performance
CMOS static RAM organized as 131,072 words by 8 bits. Easy
memory expansion is provided by an active LOW Chip Enable
(CE₁), an active HIGH Chip Enable (CE₂), an active LOW
Output Enable (OE), and three-state drivers. Writing to the
device is accomplished by taking Chip Enable One (CE₁) and
Write Enable (WE) inputs LOW and Chip Enable Two (CE₂)
input HIGH. Data on the eight I/O pins (I/O₀ through I/O₇) is
then written into the location specified on the address pins (A₀
through A₁₆).
Reading from the device is accomplished by taking Chip
Enable One (CE₁) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable Two (CE₂) HIGH. Under
these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O₀ through I/O₇) are placed in a
high-impedance state when the device is deselected (CE₁
HIGH or CE₂ LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE₁ LOW, CE₂ HIGH, and WE LOW).
The CY7C109BN is available in standard 400-mil-wide SOJ
and 32-pin TSOP type I packages. The CY7C1009BN is
available in a 300-mil-wide SOJ package. The CY7C1009BN
and CY7C109BN are functionally equivalent in all other
respects.
Logic Block Diagram
Pin Configurations
SOJ
Top View
A₀
A₁
A₂
A₃
A₄
A₅
A₆
A₇
A₈
CE₁
CE₂
WE
OE
INPUT BUFFER
512 x 256 x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
I/O₀
I/O₁
I/O₂
I/O₃
A₁₁
A₉
1
2
A₈
3
I/O₄ ^A13
WE
4
5
CE₂
6
I/O₅ A₁₅
7
V_CC
8
NC
9
I/O₆ A16
10
A₁₄
11
A₁₂
12
I/O₇ ^A7
13
A₆
14
A₅
15
A₄
16
NC 1
A_{16 2}
A₁₄ 3
A₁₂ 4
A7 5
A6 6
A5 ₇
A4 8
A3 9
A2 10
A1 ₁₁
A0 12
I/O_{0 13}
I/O_{1 14}
I/O_{2 15}
GND ₁₆
32 VCC
31 A₁₅
30 CE₂
29 WE
28 _A13
27 _A8
26 _A9
25 _A11
24 _OE
23 A₁₀
22 CE₁
21 I/O7
20 ^I/O6
19 ^I/O5
18 ^I/O4
17 I/O3
TSOP I
Top View
(not to scale)
32 OE
31
A₁₀
30 CE
29 I/O₇
28 I/O₆
27 I/O₅
26 I/O₄
25 I/O₃
24 GND
23 I/O₂
22 I/O₁
21 I/O₀
20 A₀
19 A₁
18 A₂
17 A₃
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-06430 Rev. **
Revised February 1, 2006
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