CY7C109 Datasheet, PDF (1/12 Pages) Cypress Semiconductor – 128K x 8 Static RAM

009
CY7C109
CY7C1009
128K x 8 Static RAM
Features
• High speed
— t_AA = 10 ns
• Low active power
— 1017 mW (max., 12 ns)
• Low CMOS standby power
— 55 mW (max.), 4 mW (Low power version)
• 2.0V Data Retention (Low power version)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE₁, CE₂, and OE options
Functional Description
The CY7C109 / CY7C1009 is a high-performance CMOS stat-
ic RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW chip enable (CE₁), an
active HIGH chip enable (CE₂), an active LOW output enable
(OE), and three-state drivers. Writing to the device is accom-
plished by taking chip enable one (CE₁) and write enable (WE)
inputs LOW and chip enable two (CE₂) input HIGH. Data on
the eight I/O pins (I/O₀ through I/O₇) is then written into the
location specified on the address pins (A₀ through A₁₆).
Reading from the device is accomplished by taking chip en-
able one (CE₁) and output enable (OE) LOW while forcing
write enable (WE) and chip enable two (CE₂) HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O₀ through I/O₇) are placed in a
high-impedance state when the device is deselected (CE₁
HIGH or CE₂ LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE₁ LOW, CE₂ HIGH, and WE LOW).
The CY7C109 is available in standard 400-mil-wide SOJ and
32-pin TSOP type I packages. The CY7C1009 is available in
a 300-mil-wide SOJ package. The CY7C1009 and CY7C109
are functionally equivalent in all other respects.
Logic Block Diagram
INPUT BUFFER
A₀
A₁
A₂
A₃
A₄
A₅
A₆
512 x 256 x 8
ARRAY
A₇
A₈
CE₁
CE₂
COLUMN
DECODER
POWER
DOWN
WE
OE
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Maximum CMOS Standby Current (mA)
Low Power Version
Shaded areas contain preliminary information.
7C109-10
7C1009-10
10
195
10
2
I/O₀
I/O₁
I/O₂
I/O₃
A₁₁
A₉
1
2
A₈
3
I/O₄ ^A13
WE
4
5
CE₂
6
I/O₅ A₁₅
7
V_CC
8
NC
9
I/O₆ A16
10
A₁₄
11
A₁₂
12
I/O₇ ^A7
13
A₆
14
109–1
A₅
15
A₄
16
7C109-12
7C1009-12
12
185
10
2
7C109-15
7C1009-15
15
155
10
2
Pin Configurations
SOJ
Top View
NC 1
A_{16 2}
A₁₄ 3
A₁₂ 4
A₇ 5
A₆ 6
A_{5 7}
A₄ 8
A₃ 9
A₂ 10
A_{1 11}
A₀ 12
I/O_{0 13}
I/O_{1 14}
I/O_{2 15}
GND ₁₆
32 VCC
31 A₁₅
30 CE₂
29 WE
28 _A13
27 _A8
26 _A9
25 _A11
24 _OE
23 A₁₀
22 CE₁
21 I/O7
20 ^I/O6
19 ^I/O5
18 ^I/O4
17 I/O3 _109–2
TSOP I
Top View
(not to scale)
32 OE
31
A₁₀
30 CE
29 I/O₇
28 I/O₆
27 I/O₅
26 I/O₄
25 I/O₃
24 GND
23 I/O₂
22 I/O₁
21 I/O₀
20 A₀
19 A₁
18 A₂
17 A₃
109–3
7C109-20
7C1009-20
20
140
10
—
7C109-25
7C1009-25
25
135
10
—
7C109-35
7C1009-35
35
125
10
—
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05032 Rev. **
Revised August 24, 2001