CY7C1089DV33_12 Datasheet, PDF (1/11 Pages) Cypress Semiconductor – 64-Mbit (8 M × 8) Static RAM

CY7C1089DV33
64-Mbit (8 M × 8) Static RAM
Features
■ High speed
❐ t_AA = 12 ns
■ Low active power
❐ I_CC = 300 mA at 12 ns
■ Low complementary metal oxide semiconductor (CMOS)
standby power
❐ I_SB2 = 100 mA
■ Operating voltages of 3.3 ± 0.3 V
■ 2.0-V data retention
■ Automatic power-down when deselected
■ Transistor-transistor logic (TTL)-compatible inputs and outputs
■ Easy memory expansion with CE₁ and CE₂ features
■ Available in Pb-free 48-ball fine ball grid array (FBGA) package
Functional Description
The CY7C1089DV33 is a high-performance CMOS static RAM
organized as 8,388,608 words by 8 bits.
To write to the device, take Chip Enables (CE₁ LOW and CE₂
HIGH) and Write Enable (WE) input LOW. Data on the eight I/O
pins (I/O₀ through I/O₇) is then written into the location specified
on the address pins (A₀ through A₂₂).
To read from the device, take Chip Enables (CE₁ LOW and CE₂
HIGH) LOW and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. Under these conditions, the contents
of the memory location specified by the address pins appear on
the I/O pins. See Truth Table on page 9 for a complete
description of Read and Write modes.
The input and output pins (I/O₀ through I/O₇) are placed in a high
impedance state when the device is deselected (CE₁ LOW or
CE₂ HIGH), the outputs are disabled (OE HIGH), or during a
write operation (CE₁ LOW, CE₂ HIGH and WE LOW).
Logic Block Diagram
INPUT BUFFER
A₀
A₁
A₂
A₃
A₄
A₅
8M x 8
ARRAY
A₆
A₇
A₈
A₉
COLUMN
DECODER
I/O₀ – I/O₇
WE
OE
CE₂
CE₁
Selection Guide
Description
Maximum access time
Maximum operating current
Maximum CMOS standby current
–12
Unit
12
ns
300
mA
100
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-53993 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 22, 2012