CY7C107D_1104 Datasheet, PDF (1/14 Pages) Cypress Semiconductor – 1-Mbit (1M x 1) Static RAM Low active power

CY7C107D
CY7C1007D
1-Mbit (1M x 1) Static RAM
Features
■ Pin- and function-compatible with CY7C107B/CY7C1007B
■ High speed
— t_AA = 10 ns
■ Low active power
— I_CC = 80 mA @ 10 ns
■ Low complementary metal oxide semiconductor (CMOS)
standby power
— I_SB2 = 3 mA
■ 2.0 V data retention
■ Automatic power-down when deselected
■ CMOS for optimum speed/power
■ Transistor transistor logic (TTL) compatible inputs and outputs
■ CY7C107D available in Pb-free 28-pin 400-Mil wide Molded
SOJ package. CY7C1007D available in Pb-free 28-pin 300-Mil
wide Molded SOJ package
Functional Description ^[1]
The CY7C107D and CY7C1007D are high-performance CMOS
static RAMs organized as 1,048,576 words by 1 bit. Easy
memory expansion is provided by an active LOW Chip Enable
(CE) and tri-state drivers. These devices have an automatic
power-down feature that reduces power consumption by more
than 65% when deselected. The output pin (D_OUT) is placed in a
high-impedance state when:
■ Deselected (CE HIGH)
■ When the write operation is active (CE and WE LOW)
Write to the device by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. Data on the input pin (D_IN) is written into the
memory location specified on the address pins (A₀ through A₁₉).
Read from the device by taking Chip Enable (CE) LOW while
while forcing Write Enable (WE) HIGH. Under these conditions,
the contents of the memory location specified by the address
pins appears on the data output (D_OUT) pin.
Logic Block Diagram
DIN
A0
A1
A2
A3
A4
A5
A6
A7
A8
CE
WE
INPUT BUFFER
1M x 1
ARRAY
DOUT
COLUMN DECODER
POWER
DOWN
Note
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-05469 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised April 7, 2011
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