CY7C107BN Datasheet, PDF (1/7 Pages) Cypress Semiconductor – 1M x 1 Static RAM

CY7C107BN
CY7C1007BN
1M x 1 Static RAM
Features
• High speed
— t_AA = 15 ns
• CMOS for optimum speed/power
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
Logic Block Diagram
INPUT BUFFER
A₀
A₁
A₂
A₃
A₄
512 x 2048
A₅
ARRAY
A₆
A₇
A₈
COLUMN
DECODER
POWER
DOWN
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current I_SB2 (mA)
Functional Description
The CY7C107BN and CY7C1007BN are high-performance
CMOS static RAMs organized as 1,048,576 words by 1 bit.
Easy memory expansion is provided by an active LOW Chip
Enable (CE) and three-state drivers. These devices have an
automatic power-down feature that reduces power
consumption by more than 65% when deselected.
Writing to the devices is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the input pin
(D_IN) is written into the memory location specified on the
address pins (A₀ through A₁₉).
Reading from the devices is accomplished by taking Chip
Enable (CE) LOW while Write Enable (WE) remains HIGH.
Under these conditions, the contents of the memory location
specified by the address pins will appear on the data output
(D_OUT) pin.
The output pin (D_OUT) is placed in a high-impedance state
when the device is deselected (CE HIGH) or during a write
operation (CE and WE LOW).
The CY7C107BN is available in a standard 400-mil-wide SOJ;
the CY7C1007BN is available in a standard 300-mil-wide SOJ
D_IN
D_OUT
CE
WE
Pin Configuration
SOJ
Top View
A₁₀ 1
A₁₁ 2
A₁₂ 3
A₁₃ 4
A₁₄ 5
A₁₅ 6
NC 7
A₁₆ 8
A₁₇ 9
A₁₈ 10
A₁₉ 11
D_OUT 12
WE ¹³
GND ¹⁴
28 _VCC
27 _A9
26 _A8
25
24
A₇
A₆
23 _A5
22
21
A₄
NC
20 _A3
19
18
A₂
A₁
17 _A0
16 _DIN
15 _CE
7C107BN-15
7C1007BN-15
15
80
2
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-06426 Rev. **
Revised February 1, 2006
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