CY7C1079DV33 Datasheet, PDF (1/14 Pages) Cypress Semiconductor – 32-Mbit (4 M x 8) Static RAM TTL Compatible Inputs and Outputs

CY7C1079DV33
32-Mbit (4 M × 8) Static RAM
32-Mbit (4 M × 8) Static RAM
Features
■ High Speed
❐ t_AA = 12 ns
■ Low Active Power
❐ I_CC = 250 mA at 12 ns
■ Low CMOS Standby Power
❐ I_SB2 = 50 mA
■ Operating Voltages of 3.3 ± 0.3 V
■ 2.0 V Data Retention
■ Automatic Power Down when Deselected
■ TTL Compatible Inputs and Outputs
■ Available in Pb-free 48-ball FBGA Package
Logic Block Diagram
A₀
A₁
A₂
AA₃₄
AA₅₆
AAA₇₈₉
INPUT BUFFER
4M x 8
ARRAY
COLUMN
DECODER
Functional Description
The CY7C1079DV33 is a high performance CMOS Static RAM
organized as 4,194,304 words by 8 bits.
To write to the device, take Chip Enable (CE ^[1]) and Write Enable
(WE) input LOW. Data on the eight I/O pins (I/O₀ through I/O₇)
is then written into the location specified on the address pins (A₀
through A₂₁).
To read from the device, take Chip Enable (CE ^[1]) LOW and
Output Enable (OE) LOW while forcing the Write Enable (WE)
HIGH. Under these conditions, the contents of the memory
location specified by the address pins appear on the I/O pins.
See Truth Table (Single Chip Enable) on page 9 for a complete
description of Read and Write modes.
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the outputs are disabled (OE HIGH), or during a write operation
(CE ^[1] LOW and WE LOW).
The CY7C1079DV33 is available in a 48-ball FBGA package.
IO₀ – IO₇
WE
OE
CE ^[1]
Note
1.
BGA packaged device is
CE₂ such that when CE₁
offered in single CE and dual CE options. In this data sheet, for a dual CE
is LOW and CE₂ is HIGH, CE is LOW. For all other cases CE is HIGH.
device,
CE
refers
to
the
internal
logical
combination
of
CE₁
and
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-50282 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised April 27, 2011
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