CY7C1071DV33 Datasheet, PDF (1/14 Pages) Cypress Semiconductor – 32-Mbit (2 M x 16) Static RAM TTL compatible inputs and outputs

CY7C1071DV33
32-Mbit (2 M × 16) Static RAM
32-Mbit (2 M × 16) Static RAM
Features
■ High speed
❐ t_AA = 12 ns
■ Low active power
❐ I_CC = 250 mA at 12 ns
■ Low Complementary Metal Oxide Semiconductor (CMOS)
standby power
❐ I_SB2 = 50 mA
■ Operating voltages of 3.3 ± 0.3 V
■ 2.0 V data retention
■ Automatic power down when deselected
■ TTL compatible inputs and outputs
■ Available in Pb-free 48-ball FBGA package
Functional Description
The CY7C1071DV33 is a high performance CMOS Static RAM
organized as 2,097,152 words by 16 bits. The input and output
pins (I/O₀ through I/O₁₅) are placed in a high impedance state
when:
■ Deselected (CE HIGH)
■ Outputs are disabled (OE HIGH)
■ Both byte high enable and byte low enable are disabled (BHE,
BLE HIGH)
■ The write operation is active (CE LOW and WE LOW)
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O₀ through I/O₇) is written into the location
specified on the address pins (A₀ through A₂₀). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O₈ through
I/O₁₅) is written into the location specified on the address pins
(A₀ through A₂₀).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O₀ to I/O₇. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O₈ to I/O₁₅. See the Truth Table on page 10 for a
complete description of read and write modes.
Logic Block Diagram
DATA IN DRIVERS
A_(10:0)
2M × 16
RAM ARRAY
IO₀–IO₇
IO₈–IO₁₅
COLUMN DECODER
A_(20:11)
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-12063 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 28, 2011
[+] Feedback