CY7C106BN_11 Datasheet, PDF (1/9 Pages) Cypress Semiconductor – 256K x 4 Static RAM

Features
■ High speed
❐ t_AA = 15 ns
■ CMOS for optimum speed/power
■ Low active power
❐ 495 mW
■ Low standby power
❐ 275 mW
■ 2.0V data retention (optional)
■ Automatic power down when deselected
■ TTL-compatible inputs and outputs
Logic Block Diagram
CY7C106BN
256K x 4 Static RAM
Functional Description
The CY7C106BN is a high performance CMOS static RAMs
organized as 262,144 words by 4 bits. Easy memory expansion
is provided by an active LOW Chip Enable (CE), an active LOW
Output Enable (OE), and tristate drivers. These devices have an
automatic power down feature that reduces power consumption
by more than 65% when the devices are deselected.
Writing to the devices is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the four I/O
pins (I/O₀ through I/O₃) is then written into the location specified
on the address pins (A₀ through A₁₇).
Reading from the devices is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while forcing Write Enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins will appear on the four I/O
pins.
The four input/output pins (I/O₀ through I/O₃) are placed in a high
impedance state when the devices are deselected (CE HIGH),
the outputs are disabled (OE HIGH), or during a write operation
(CE and WE LOW).
The CY7C106BN is available in a standard 400-mil-wide SOJ.
INPUT BUFFER
A₁
A₂
A₃
A₄
A₅
512 x 512 x 4
A₆
ARRAY
A₇
A₈
A₉
COLUMN
DECODER
POWER
DOWN
I/O₃
I/O₂
I/O₁
I/O₀
CE
WE
OE
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-06429 Rev. *A
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 15, 2010
[+] Feedback