CY7C1069GN Datasheet, PDF (1/15 Pages) Cypress Semiconductor – 16-Mbit (2M × 8) Static RAM

CY7C1069GN
16-Mbit (2M × 8) Static RAM
16-Mbit (2M × 8) Static RAM
Features
■ High speed
❐ t_AA = 10 ns
■ Low active power
❐ I_CC = 90 mA at 100 MHz
■ Low complementary metal oxide semiconductor (CMOS)
standby power
❐ I_SB2 = 20 mA (typical)
■ Operating voltages of 2.2 V to 3.6 V
■ 1.0 V data retention
■ Automatic power-down when deselected
■ Transistor-transistor logic (TTL) compatible inputs and outputs
■ Easy memory expansion with CE₁ and CE₂ features
■ Available in Pb-free 54-pin thin small outline package (TSOP)
Type II and 48-ball very fine-pitch ball grid array (VFBGA)
packages.
Functional Description
The CY7C1069GN is a high performance CMOS Static RAM
organized as 2,097,152 words by 8 bits.
To write to the device, take Chip Enables (CE₁ LOW and CE₂
HIGH) and Write Enable (WE) input LOW. Data on the eight I/O
pins (I/O₀ through I/O₇) is then written into the location specified
on the address pins (A₀ through A₂₀).
To read from the device, take Chip Enables (CE₁ LOW and CE₂
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. Under these conditions, the contents of the
memory location specified by the address pins will appear on the
I/O pins. See Truth Table on page 10 for a complete description
of Read and Write modes.
The input and output pins (I/O₀ through I/O₇) are placed in a high
impedance state when the device is deselected (CE₁ HIGH or
CE₂ LOW), the outputs are disabled (OE HIGH), or during a write
operation (CE₁ LOW, CE₂ HIGH, and WE LOW).
The CY7C1069GN is available in a 54-pin TSOP II and a 48-ball
very fine-pitch ball grid array (VFBGA) package.
Logic Block Diagram
INPUT BUFFER
A₀
A₁
A₂
AA₃₄
A₅
2Mx8
ARRAY
A₆
AAA₇₈₉
COLUMN
DECODER
I/O₀ – I/O₇
WE
CE₂
OE
CE₁
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-00046 Rev. *A
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 15, 2016