CY7C1069AV33_12 Datasheet, PDF (1/12 Pages) Cypress Semiconductor – 2 M × 8 Static RAM

CY7C1069AV33
2 M × 8 Static RAM
2 M × 8 Static RAM
Features
■ High speed
❐ t_AA = 10 ns
■ Low active power
❐ 990 mW (max)
■ Operating voltages of 3.3 ± 0.3 V
■ 2.0 V data retention
■ Automatic power down when deselected
■ TTL-compatible inputs and outputs
■ Easy memory expansion with CE₁ and CE₂ features
■ Available in Pb-free 54-pin thin small outline package (TSOP) II
package
Functional Description
The CY7C1069AV33 is a high performance complementary
metal oxide semiconductor (CMOS) static RAM organized as
2,097,152 words by 8 bits. Writing to the device is accomplished
by enabling the chip (by taking CE₁ LOW and CE₂ HIGH) and
Write Enable (WE) inputs LOW.
Reading from the device is accomplished by enabling the chip
(CE₁ LOW and CE₂ HIGH) as well as forcing the Output Enable
(OE) LOW while forcing the WE HIGH. See “Truth Table” on
page 8 for a complete description of Read and Write modes.
The input/output pins (I/O₀ through I/O₇) are placed in a high
impedance state when the device is deselected (CE₁ HIGH or
CE₂ LOW), the outputs are disabled (OE HIGH), or during a
Write operation (CE₁ LOW, CE₂ HIGH, and WE LOW).
The CY7C1069AV33 is available in a 54-pin TSOP II package
with center power and ground (revolutionary) pinout.
Logic Block Diagram
I/O₀
Data in Drivers
AAAAAAAAAAAAA_{1119123045217860}
2048K x 8
ARRAY
I/O₁
I/O₂
I/O₃
I/O₄
I/O₅
CE₁
CE₂
WE
COLUMN
DECODER
POWER
DOWN
I/O₆
I/O₇
OE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05255 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 29, 2010
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