CY7C1062DV33 Datasheet, PDF (1/10 Pages) Cypress Semiconductor – 16-Mbit (512K X 32) Static RAM

PRELIMINARY
CY7C1062DV33
16-Mbit (512K X 32) Static RAM
Features
• High speed
— t_AA = 10 ns
• Low active power
— I_CC = 150 mA @ 10 ns
• Low CMOS standby power
— I_SB2 = 25 mA
• Operating voltages of 3.3 ± 0.3V
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE₁, CE₂, and CE₃
features
• Available in Pb-free 119-ball plastic ball grid array
(PBGA) package
Logic Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
INPUT BUFFERS
512K x 32
ARRAY
COLUMN
DECODER
Functional Description
The CY7C1062DV33 is a high-performance CMOS Static
RAM organized as 524,288 words by 32 bits.
Writing to the device is accomplished by enabling the chip
(CE_1, CE₂ and CE₃ LOW) and forcing the Write Enable (WE)
input LOW. If Byte Enable A (B_A) is LOW, then data from I/O
pins (I/O₀ through I/O₇), is written into the location specified on
the address pins (A₀ through A₁₈). If Byte Enable B (B_B) is
LOW, then data from I/O pins (I/O₈ through I/O₁₅) is written into
the location specified on the address pins (A₀ through A₁₈).
Likewise, B_C and B_D correspond with the I/O pins I/O₁₆ to I/O₂₃
and I/O₂₄ to I/O₃₁, respectively.
Reading from the device is accomplished by enabling the chip
(CE_1, CE₂, and CE₃ LOW) while forcing the Output Enable
(OE) LOW and Write Enable (WE) HIGH. If the first Byte
Enable (B_A) is LOW, then data from the memory location
specified by the address pins will appear on I/O₀ to I/O₇. If Byte
Enable B (B_B) is LOW, then data from memory will appear on
I/O₈ to I/O₁₅. Similarly, B_c and B_D correspond to the third and
fourth bytes. See the truth table at the back of this data sheet
for a complete description of read and write modes.
The input/output pins (I/O₀ through I/O₃₁) are placed in a
high-impedance state when the device is deselected (CE_1,
CE₂or CE₃ HIGH), the outputs are disabled (OE HIGH), the
byte selects are disabled (B_A-D HIGH), or during a write
operation (CE_1, CE₂, and CE₃ LOW, and WE LOW).
The CY7C1062DV33 is available in 119-ball plastic ball grid
array (PBGA) package.
WE
CE₁
CE₂
CE₃
OE
B_A
B_B
B_C
B_D
I/O₀–I/O₃₁
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05477 Rev.*C
Revised September 4, 2006
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