CY7C1062DV33-10BGI Datasheet, PDF (1/15 Pages) Cypress Semiconductor – 16-Mbit (512 K x 32) Static RAM

CY7C1062DV33
16-Mbit (512 K × 32) Static RAM
16-Mbit (512 K × 32) Static RAM
Features
■ High speed
❐ t_AA = 10 ns
■ Low active power
❐ I_CC = 175 mA at 100 MHz
■ Low complementary metal oxide semiconductor (CMOS)
standby power
❐ I_SB2 = 25 mA
■ Operating voltages of 3.3 ± 0.3 V
■ 2.0 V data retention
■ Automatic power down when deselected
■ Transistor-transistor logic (TTL) compatible inputs and outputs
■ Easy memory expansion with CE₁, CE₂, and CE₃ features
■ Available in Pb-free 119-ball plastic ball grid array (PBGA)
package
Logic Block Diagram
INPUT BUFFERS
A_(9:0)
512 K x 32
ARRAY
Functional Description
The CY7C1062DV33 is a high performance CMOS Static RAM
organized as 524,288 words by 32 bits.
To write to the device, take Chip Enables (CE_1, CE_2, and CE₃
LOW) and Write Enable (WE) input LOW. If Byte Enable A (B_A)
is LOW, then data from I/O pins (I/O₀ through I/O₇) is written into
the location specified on the address pins (A₀ through A₁₈). If
Byte Enable B (B_B) is LOW, then data from I/O pins (I/O₈ through
I/O₁₅) is written into the location specified on the address pins
(A₀ through A₁₈). Likewise, B_C and B_D correspond with the I/O
pins I/O₁₆ to I/O₂₃ and I/O₂₄ to I/O₃₁, respectively.
To read from the device, take Chip Enables (CE_1, CE₂, and CE₃
LOW) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If the first B_A is LOW, then data from the
memory location specified by the address pins appear on I/O₀ to
I/O₇. If B_B is LOW, then data from memory appears on I/O₈ to
I/O₁₅. Likewise, B_c and B_D correspond to the third and fourth
bytes. See Truth Table on page 10 for a complete description of
read and write modes.
The input and output pins (I/O₀ through I/O₃₁) are placed in a
high impedance state when the device is deselected (CE_1, CE_2,
or CE₃ HIGH), the outputs are disabled (OE HIGH), the byte
selects are disabled (B_A-D HIGH), or during a write operation
(CE_1, CE₂ and CE₃ LOW and WE LOW).
WE
CE₁
CE₂
CE₃
OE
B_A
B_B
B_C
B_D
I/O₀–I/O₃₁
COLUMN
DECODER
A_(18:10)
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05477 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 20, 2011
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