CY7C1062AV33_06 Datasheet, PDF (1/9 Pages) Cypress Semiconductor – 512K x 32 Static RAM

CY7C1062AV33
512K x 32 Static RAM
Features
• High speed
— t_AA = 8 ns
• Low active power
— 1080 mW (max.)
• Operating voltages of 3.3 ± 0.3V
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE₁, CE₂, and CE₃
features
• Available in non Pb-free 119-ball PBGA package
Functional Description
The CY7C1062AV33 is a high-performance CMOS Static
RAM organized as 524,288 words by 32 bits.
Writing to the device is accomplished by enabling the chip
(CE_1, CE₂, and CE₃ LOW) and forcing the Write Enable (WE)
input LOW. If Byte Enable A (B_A) is LOW, then data from I/O
Logic Block Diagram
INPUT BUFFERS
A₀
A₁
A₂
A₃
A₄
512K x 32
ARRAY
A₅
A₆
A₇
A₈
A₉
pins (I/O₀ through I/O₇), is written into the location specified on
the address pins (A₀ through A₁₈). If Byte Enable B (B_B) is
LOW, then data from I/O pins (I/O₈ through I/O₁₅) is written into
the location specified on the address pins (A₀ through A₁₈).
Likewise, B_C and B_D correspond with the I/O pins I/O₁₆ to I/O₂₃
and I/O₂₄ to I/O₃₁, respectively.
Reading from the device is accomplished by enabling the chip
(CE_1, CE₂, and CE₃ LOW) while forcing the Output Enable
(OE) LOW and Write Enable (WE) HIGH. If the first Byte
Enable (B_A) is LOW, then data from the memory location
specified by the address pins will appear on I/O₀ to I/O₇. If Byte
Enable B (B_B) is LOW, then data from memory will appear on
I/O₈ to I/O₁₅. Similarly, B_c and B_D correspond to the third and
fourth bytes. See the truth table at the back of this data sheet
for a complete description of read and write modes.
The input/output pins (I/O₀ through I/O₃₁) are placed in a
high-impedance state when the device is deselected (CE_1,
CE₂or CE₃ HIGH), the outputs are disabled (OE HIGH), the
byte selects are disabled (B_A-D HIGH), or during a write
operation (CE_1, CE₂, and CE₃ LOW, and WE LOW).
The CY7C1062AV33 is available in a 119-ball pitch ball grid
array (PBGA) package.
WE
CE₁
CE₂
CE₃
OE
B_A
B_B
B_C
B_D
I/O₀–I/O₃₁
COLUMN
DECODER
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
–8
–10
–12
Unit
8
10
12
ns
Com’l
300
275
260
mA
Ind’l
300
275
260
Com’l/Ind’l
50
50
50
mA
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05137 Rev. *F
Revised August 3, 2006
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