CY7C1061G Datasheet, PDF (1/18 Pages) Cypress Semiconductor – 16-Mbit (1 M words × 16 bit) Static RAM with Error-Correcting Code (ECC)

CY7C1061G Automotive
16-Mbit (1 M words × 16 bit) Static RAM
with Error-Correcting Code (ECC)
16-Mbit (1 M words × 16 bit) Static RAM with Error-Correcting Code (ECC)
Features
■ High speed
❐ t_AA = 10 ns
■ Temperature range
❐ Automotive-E: –40 °C to 125 °C
■ Embedded error-correcting code (ECC) for single-bit error
correction
■ Low active and standby currents
❐ I_CC = 90-mA typical at 100 MHz
❐ I_SB2 = 20-mA typical
■ Operating voltage range: 2.2 V to 3.6 V
■ 1.0-V data retention
■ Transistor-transistor logic (TTL) compatible inputs and outputs
■ Available in Pb-free 48-ball VFBGA and 48-pin TSOP I
packages
Functional Description
CY7C1061G^[1] is a high-performance CMOS fast static RAM
automotive part with embedded ECC. ECC logic can detect and
correct single-bit error in read data word during read cycles.
This device has single chip enable input and is accessed by
asserting the chip enable input (CE) LOW.
To perform data writes, assert the Write Enable (WE) input LOW
and provide the data and address on the device data pins (I/O₀
through I/O₁₅) and address pins (A₀ through A₁₉) respectively.
The Byte High Enable (BHE) and Byte Low Enable (BLE), inputs
control byte writes and write data on the corresponding I/O lines
to the memory location specified. BHE controls I/O₈ through
I/O₁₅ and BLE controls I/O₀ through I/O₇.
To perform data reads, assert the Output Enable (OE) input and
provide the required address on the address lines. Read data is
accessible on I/O lines (I/O₀ through I/O₁₅). You can perform
byte accesses by asserting the required byte enable signal (BHE
or BLE) to read either the upper byte or the lower byte of data
from the specified address location.
All I/Os (I/O₀ through I/O₁₅) are placed in a high-impedance state
when the device is deselected (CE HIGH), or control signals are
de-asserted (OE, BLE, BHE). Refer to the below logic block
diagram.
The CY7C1061G automotive device is available in 48-ball
VFBGA and 48-pin TSOP I packages.
Logic Block Diagram – CY7C1061G
ECC ENCODER
INPUT BU FFER
A0
A1
A2
A3
A4
M EM ORY
A5
ARRAY
A6
A7
A8
A9
COLUM N DECODER
I/O 0‐I/O 7
I/O 8‐I/O 15
Note
1. The device does not support automatic write-back on error detection.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-84821 Rev. *H
BHE
WE
OE
CE
BLE
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 28, 2015