CY7C1061BV33 Datasheet, PDF(1/9 Page) Cypress Semiconductor

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CY7C1061BV33 Datasheet, PDF (1/9 Pages) Cypress Semiconductor – 16-Mbit (1M x 16) Static RAM

CY7C1061BV33

16-Mbit (1M x 16) Static RAM

Features

â¢ High speed

â tAA = 10 ns

â¢ Low active power

â 990 mW (max.)

â¢ Operating voltages of 3.3 Â± 0.3V

â¢ 2.0V data retention

â¢ Automatic power-down when deselected

â¢ TTL-compatible inputs and outputs

â¢ Available in Pb-free and non Pb-free 54-pin TSOP II

package

Functional Description

The CY7C1061BV33 is a high-performance CMOS Static

RAM organized as 1,048,576 words by 16 bits.

Writing to the device is accomplished by enabling the chip (CE

LOW) while forcing the Write Enable (WE) input LOW. If Byte

Low Enable (BLE) is LOW, then data from I/O pins (I/O0

through I/O7), is written into the location specified on the

address pins (A0 through A19). If Byte High Enable (BHE) is

LOW, then data from I/O pins (I/O8 through I/O15) is written into

the location specified on the address pins (A0 through A19).

Reading from the device is accomplished by enabling the chip

by taking CE LOW while forcing the Output Enable (OE) LOW

and the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is

LOW, then data from the memory location specified by the

address pins will appear on I/O0 to I/O7. If Byte High Enable

(BHE) is LOW, then data from memory will appear on I/O8 to

I/O15. See the truth table at the back of this data sheet for a

complete description of Read and Write modes.

The input/output pins (I/O0 through I/O15) are placed in a

high-impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), the BHE and BLE

are disabled (BHE, BLE HIGH), or during a Write operation

(CE LOW and WE LOW).

The CY7C1061BV33 is available in a 54-pin TSOP II package

with center power and ground (revolutionary) pinout.

Logic Block Diagram

Pin Configurations[1, 2]

54-pin TSOP II (Top View)

INPUT BUFFER

1M x 16

ARRAY

COLUMN

DECODER

I/O0âI/O7

I/O8âI/O15

BHE

BLE

I/O12 1

VCC 2

I/O13 3

I/O14 4

VSS 5

I/O15 6

A4 7

A3 8

A2 9

A1 10

A0 11

BHE 12

CE 13

VCC 14

WE 15

DNU/VCC 16

A19 17

A18 18

A17 19

A16 20

A15 21

I/O0 22

VCC 23

I/O1 24

I/O2 25

VSS 26

I/O3 27

54 I/O11

53 VSS

52 I/O10

51 I/O9

50 VCC

49 I/O8

48 A5

47 A6

46 A7

45 A8

44 A9

43 NC

42 OE

41 VSS

40 DNU/VSS

39 BLE

38 A10

37 A11

36 A12

35 A13

34 A14

33 I/O7

32 VSS

31 I/O6

30 I/O5

29 VCC

28 I/O4

Notes:

1. DNU/VCC Pin (#16) has to be left floating or connected to VCC and DNU/VSS Pin (#40) has to be left floating or connected to VSS to ensure proper application.

2. NC â No Connect Pins are not connected to the die

Cypress Semiconductor Corporation â¢ 198 Champion Court â¢ San Jose, CA 95134-1709 â¢ 408-943-2600

Document #: 38-05693 Rev. *B

Revised August 3, 2006

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