CY7C1061AV33_07 Datasheet, PDF (1/10 Pages) Cypress Semiconductor – 16-Mbit (1M x 16) Static RAM

CY7C1061AV33
16-Mbit (1M x 16) Static RAM
Features
• High speed
— t_AA = 10 ns
• Low active power
— 990 mW (max)
• Operating voltages of 3.3 ± 0.3V
• 2.0V data retention
• Automatic power down when deselected
• TTL compatible inputs and outputs
• Easy memory expansion with CE₁ and CE₂ features
• Available in Pb-free and non Pb-free 54-pin TSOP II
package and non Pb-free 60-ball fine pitch ball grid array
(FBGA) package
Logic Block Diagram
Functional Description
The CY7C1061AV33 is a high performance CMOS Static RAM
organized as 1,048,576 words by 16 bits.
To write to the device, enable the chip (CE₁ LOW and CE₂
HIGH) while forcing the Write Enable (WE) input LOW. If Byte
Low Enable (BLE) is LOW, then data from IO pins (IO₀ through
IO₇), is written into the location specified on the address pins
(A₀ through A₁₉). If Byte High Enable (BHE) is LOW, then data
from IO pins (IO₈ through IO₁₅) is written into the location
specified on the address pins (A₀ through A₁₉).
To read from the device, enable the chip by taking CE₁ LOW
and CE₂ HIGH while forcing the Output Enable (OE) LOW and
the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is
LOW, then data from the memory location specified by the
address pins will appear on IO₀ to IO₇. If Byte High Enable
(BHE) is LOW, then data from memory will appear on IO₈ to
IO₁₅. See “Truth Table” on page 7 for a complete description
of Read and Write modes.
The input/output pins (IO₀ through IO₁₅) are placed in a
high-impedance state when the device is deselected (CE₁
HIGH/CE₂ LOW), the outputs are disabled (OE HIGH), the
BHE and BLE are disabled (BHE, BLE HIGH), or a Write
operation is in progress (CE₁ LOW, CE₂ HIGH, and WE LOW).
INPUT BUFFER
A₀
A₁
A₂
A₃
A₄
A₅
1M x 16
ARRAY
A₆
A₇
A₈
A₉
COLUMN
DECODER
IO₀–IO₇
IO₈–IO₁₅
BHE
WE
CE₂
OE
CE₁
BLE
Cypress Semiconductor Corporation
Document #: 38-05256 Rev. *G
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised March 26, 2007
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