CY7C1061AV25 Datasheet, PDF (1/11 Pages) Cypress Semiconductor – 1M x 16 Static RAM

PRELIMINARY
CY7C1061AV25
1M x 16 Static RAM
Features
• High speed
— t_AA = 8, 10, 12 ns
• Low active power
— 1080 mW (max.)
• Operating voltages of 2.5 ± 0.2V
• 1.5V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE₁ and CE₂ features
Functional Description
The CY7C1061AV25 is a high-performance CMOS Static
RAM organized as 1,048,576 words by 16 bits.
Writing to the device is accomplished by enabling the chip
(CE₁ LOW and CE₂ HIGH) while forcing the Write Enable
(WE) input LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O₀ through I/O₇), is written into the location
specified on the address pins (A₀ through A₁₉). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O₈ through
I/O₁₅) is written into the location specified on the address pins
(A₀ through A₁₉).
Reading from the device is accomplished by enabling the chip
by taking CE₁ LOW and CE₂ HIGH while forcing the Output
Enable (OE) LOW and the Write Enable (WE) HIGH. If Byte
Low Enable (BLE) is LOW, then data from the memory location
specified by the address pins will appear on I/O₀ to I/O₇. If Byte
High Enable (BHE) is LOW, then data from memory will appear
on I/O₈ to I/O₁₅. See the truth table at the back of this data
sheet for a complete description of Read and Write modes.
The input/output pins (I/O₀ through I/O₁₅) are placed in a
high-impedance state when the device is deselected (CE₁
HIGH / CE₂ LOW), the outputs are disabled (OE HIGH), the
BHE and BLE are disabled (BHE, BLE HIGH), or during a
Write operation (CE₁ LOW, CE₂ HIGH, and WE LOW).
The CY7C1061AV25 is available in a 54-pin TSOP II package
with center power and ground (revolutionary) pinout, and a
48-ball fine-pitch ball grid array (FBGA) package.
Logic Block Diagram
INPUT BUFFER
A₀
A₁
A₂
A₃
A₄
A₅
A₆
1M x 16
ARRAY
4096 x 4096
A₇
A₈
A₉
COLUMN
DECODER
I/O₀–I/O₇
I/O₈–I/O₁₅
BHE
WE
CE₂
OCEE¹
BLE
Pin Configuration
TSOP II (Top View)
I/O₁₂ 1
V_CC 2
I/O₁₃ 3
I/O₁₄ 4
V_{SS 5}
I/O₁₅ 6
A₄ 7
A₃ 8
A₂ 9
A₁ 10
A₀ 11
BHE 12
CE₁ 13
V_{CC 14}
WE 15
CE_{2 16}
A₁₉ 17
A₁₈ 18
A₁₇ 19
A₁₆ 20
A₁₅ 21
I/O₀ 22
V_CC 23
I/O₁ ²⁴
I/O₂ 25
V_SS 26
I/O₃ 27
54 I/O₁₁
53 V_SS
52 I/O₁₀
51 I/O₉
50 V_CC
49 I/O₈
48 A₅
47 A₆
46 A₇
45 A₈
44 A₉
43 NC
42 _OE
41 V_SS
40 DNU (Do Not Use)
39 BLE
38 A₁₀
37 A₁₁
36 A₁₂
35 A₁₃
34 A₁₄
33 _I/O7
32 V_SS
31 I/O₆
30 I/O₅
29 V_CC
28 I/O₄
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Commercial
Industrial
Commercial/Industrial
-8
-10
-12
Unit
8
10
12
ns
300
275
260
mA
300
275
260
50
50
50
mA
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05331 Rev. **
Revised January 27, 2003