CY7C1059DV33_09 Datasheet, PDF (1/10 Pages) Cypress Semiconductor – 8-Mbit (1M x 8) Static RAM

Features
■ High speed
❐ t_AA = 10 ns
■ Low active power
❐ I_CC = 110 mA at 10 ns
■ Low CMOS standby power
❐ I_SB2 = 20 mA
■ 2.0V data retention
■ Automatic power down when deselected
■ TTL-compatible inputs and outputs
■ Easy memory expansion with CE and OE features
■ Available in Pb-free 44-pin TSOP II package
■ Offered in standard and high reliability (Q) grades
Logic Block Diagram
CY7C1059DV33
8-Mbit (1M x 8) Static RAM
Functional Description
The CY7C1059DV33^[1] is a high performance CMOS Static RAM
organized as 1M words by 8 bits. Easy memory expansion is
provided by an active LOW Chip Enable (CE), an active LOW
Output Enable (OE), and tri-state drivers. To write to the device,
take Chip Enable (CE) and Write Enable (WE) inputs LOW. Data
on the eight IO pins (IO₀ through IO₇) is then written into the
location specified on the address pins (A₀ through A₁₉).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins appear on the IO pins.
The eight input or output pins (IO₀ through IO₇) are placed in a
high impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), or a write operation is in
progress (CE LOW and WE LOW).
The CY7C1059DV33 is available in 36-ball FBGA and 44-pin
TSOP II packages with center power and ground (revolutionary)
pinout.
A0
INPUT BUFFER
IO0
A1
A2
IO1
A3
A4
IO2
A5
A6
1M x 8
IO3
A7
A8
ARRAY
IO4
A9
A10
IO5
IO6
CE
WE
COLUMN DECODER
POWER
DOWN
IO7
OE
Note
1. For guidelines about SRAM system design, refer to the Cypress application note AN1064, SRAM System Guidelines available at www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-00061 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 20, 2008
[+] Feedback