CY7C1049DV33_07 Datasheet, PDF (1/10 Pages) Cypress Semiconductor – 4-Mbit (512K x 8) Static RAM

CY7C1049DV33
4-Mbit (512K x 8) Static RAM
Features
■ Pin and function compatible with CY7C1049CV33
■ High speed
❐ t_AA = 10 ns
■ Low active power
❐ I_CC = 90 mA @ 10 ns (Industrial)
■ Low CMOS standby power
❐ I_SB2 = 10 mA
■ 2.0V data retention
■ Automatic power down when deselected
■ TTL compatible inputs and outputs
■ Easy memory expansion with CE and OE features
■ Available in Pb-free 36-pin (400 Mil) Molded SOJ and 44-pin
TSOP II packages
Functional Description
The CY7C1049DV33 is a high performance CMOS Static RAM
organized as 512K words by 8-bits. Easy memory expansion is
provided by an Active LOW Chip Enable (CE), an Active LOW
Output Enable (OE), and tri-state drivers. You can write to the
device by taking Chip Enable (CE) and Write Enable (WE) inputs
LOW. Data on the eight IO pins (IO₀ through IO₇) is then written
into the location specified on the address pins (A₀ through A₁₈).
You can read from the device by taking Chip Enable (CE) and
Output Enable (OE) LOW while forcing Write Enable (WE) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins appear on the IO pins.
The eight input or output pins (IO₀ through IO₇) are placed in a
high impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), or during a write operation
(CE LOW, and WE LOW).
The CY7C1049DV33 is available in standard 400 Mil wide 36
-pin SOJ package and 44-pin TSOP II package with center
power and ground (revolutionary) pinout.
Refer to the Cypress application note AN1064, SRAM System
Guidelines for best practice recommendations.
Logic Block Diagram
INPUT BUFFER
IO0
A0
A1
IO1
A2
A3
IO2
A4
512K x 8
A5
IO3
A6
ARRAY
A7
IO4
A8
A9
IO5
A10
IO6
CE
WE
COLUMN DECODER
POWER
DOWN
IO7
OE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05475 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 23, 2007