CY7C1049DV33 Datasheet, PDF (1/8 Pages) Cypress Semiconductor – 4-Mbit (512K x 8) Static RAM

CY7C1049DV33
4-Mbit (512K x 8) Static RAM
Features
• Pin- and function-compatible with CY7C1049CV33
• High speed
— t_AA = 10 ns
• Low active power
— I_CC = 90 mA @ 10 ns (Industrial)
• Low CMOS standby power
— I_SB2 = 10 mA
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
• Available in Lead-Free 36-lead (400-mil) Molded SOJ
V36 and 44-pin TSOP II ZS44 packages
Functional Description^[1]
The CY7C1049DV33 is a high-performance CMOS Static
RAM organized as 512K words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and tri-state drivers. Writing
to the device is accomplished by taking Chip Enable (CE) and
Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O₀
through I/O₇) is then written into the location specified on the
address pins (A₀ through A₁₈).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O₀ through I/O₇) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a Write
operation (CE LOW, and WE LOW).
The CY7C1049DV33 is available in standard 400-mil-wide
36-pin SOJ package and 44-pin TSOP II package with center
power and ground (revolutionary) pinout.
Logic Block Diagram
A₀
A₁
A₂
A₃
A₄
A₅
A₆
A₇
A₈
A₉
A₁₀
CE
WE
OE
INPUTBUFFER
512K x 8
COLUMN
DECODER
POWER
DOWN
Pin Configuration
SOJ
Top View
TSOP II
Top View
A₀ 1
A_{1 2}
A₂ 3
A₃ 4
36 _NC
35 _A18
34 _A17
33 _A16
NC 1
NC 2
A₀ 3
A₁ 4
A₂ 5
44 _NC
43 _NC
42 _NC
41 A₁₈
40 _A17
I/O₀
A_{4 5}
CE ₆
32 A₁₅
31 _OE
A₃ 6
A₄ 7
39 _A16
38 _A15
I/O₁
I/O₂
I/O₃
I/O₀ 7
I/O₁ 8
V_CC 9
GND 10
I/O₂ 11
30 I/O₇
29 _I/O6
28 _GND
27 _VCC
26 I/O₅
CE 8
I/O₀ 9
I/O₁ 10
V_CC 11
V_SS 12
I/O₂ 13
37 _OE
36 _I/O7
35 _I/O6
34 _VSS
33 _VCC
32 I/O₅
I/O₄
I/O3 12
25 I/O₄
I/O_{3 14}
31 I/O₄
I/O₅
I/O₆
WE 13
A₅ 14
A₆ 15
A₇ 16
24 A₁₄
23 A₁₃
22 A₁₂
21 _A11
WE 15
A₅ 16
A₆ 17
A₇ ¹⁸
A₈ 19
30 A₁₄
29 A₁₃
28 _A12
27 A₁₁
26 A₁₀
I/O₇
A_{8 17}
A_{9 18}
20 A₁₀
19 NC
A₉ 20
NC 21
25 NC
24 NC
NC 22
23 NC
Selection Guide
-10 (Industrial)
-12 (Automotive)^[2]
Unit
Maximum Access Time
10
12
ns
Maximum Operating Current
90
95
mA
Maximum CMOS Standby Current
10
15
mA
Notes:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
2. Automotive product information is Preliminary.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05475 Rev. *C
Revised April 3, 2006
[+] Feedback