CY7C1049CV33 Datasheet, PDF (1/9 Pages) Cypress Semiconductor – 512K x 8 Static RAM

CY7C1049CV33
4-Mbit (512K x 8) Static RAM
Features
• Temperature Ranges
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive: –40°C to 125°C
• High speed
— t_AA = 10 ns
• Low active power
— 324 mW (max.)
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
Logic Block Diagram
A₀
A₁
A₂
A₃
A₄
A₅
A₆
A₇
A₈
A₉
A₁₀
CE
WE
OE
INPUT BUFFER
512K x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
Functional Description^[1]
The CY7C1049CV33 is a high-performance CMOS Static
RAM organized as 524,288 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O₀ through I/O₇) is then written into the location
specified on the address pins (A₀ through A₁₈).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O₀ through I/O₇) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a Write
operation (CE LOW, and WE LOW).
The CY7C1049CV33 is available in standard 400-mil-wide
36-pin SOJ package and 44-pin TSOP II package with center
power and ground (revolutionary) pinout.
Pin Configuration
SOJ
Top View
TSOP II
Top View
A₀ 1
A_{1 2}
A₂ 3
A₃ 4
I/O₀
A_{4 5}
CE ₆
I/O₁ ^I/O0 ⁷
I/O₁ 8
I/O₂ V_CC 9
GND 10
I/O₃ I/O₂ 11
I/O₃ 12
I/O_{4 WE 13}
I/O₅
A₅ 14
A₆ 15
I/O₆
A₇ 16
A_{8 17}
A_{9 18}
I/O₇
36 _NC
NC 1
35 _A18
NC 2
34 _A17
A₀ 3
33 _A16
32 A₁₅
31 _OE
A₁ 4
A_{2 5}
A₃ 6
A_{4 7}
30 _{I/O7 CE 8}
29 _{I/O6 I/O0 9}
28 _GND I/O₁ 10
27
26
25
V_CC
I/O₅
I/O₄
V_CC
V_SS
I/O₂
I/O₃
11
12
13
14
24 A₁₄ WE 15
23
22
21
20
A₁₃
A₁₂
A₁₁
A₁₀
A₅
A₆
A₇
A₈
A₉
16
17
18
19
20
19 NC ^{NC 21}
NC 22
44 _NC
43 _NC
42 _NC
41 A₁₈
40 _A17
39 _A16
38 _A15
37 _OE
36 _I/O7
35 _I/O6
34 _VSS
33 _VCC
32 I/O₅
31 I/O₄
30 A₁₄
29 A₁₃
28 _A12
27 A₁₁
26 A₁₀
25 NC
24 ^NC
23 _NC
Notes:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05006 Rev. *C
Revised July 19, 2004