CY7C1049BV33 Datasheet, PDF (1/10 Pages) Cypress Semiconductor – 512K x 8 Static RAM

049B V33
CY7C1049BV33
Features
• High speed
— t_AA = 15 ns
• Low active power
— 504 mW (max.)
• Low CMOS standby power (Commercial L version)
— 1.8 mW (max.)
• 2.0V Data Retention (660 µW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
Functional Description^[1]
The CY7C1049BV33 is a high-performance CMOS Static
RAM organized as 524,288 words by 8 bits. Easy memory
Logic Block Diagram
INPUT BUFFER
I/O₀
A₀
A₁
I/O₁
A₂
A₃
I/O₂
A₄
A₅
A₆
A₇
512K x 8
ARRAY
A₈
I/O₃
I/O₄
A₉
A₁₀
I/O₅
CE
COLUMN
DECODER
POWER
DOWN
WE
I/O₆
I/O₇
OE
512K x 8 Static RAM
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers. Writ-
ing to the device is accomplished by taking Chip Enable (CE)
and Write Enable (WE) inputs LOW. Data on the eight I/O pins
(I/O₀ through I/O₇) is then written into the location specified on
the address pins (A₀ through A₁₈).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O₀ through I/O₇) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1049BV33 is available in a standard 400-mil-wide
36-pin SOJ and 44-pin TSOPII packages with center power
and ground (revolutionary) pinout.
A₀
A₁
A₂
A₃
A₄
CE
I/O₀
I/O₁
V_CC
GND
I/O₂
I/O3
WE
A₅
A₆
A₇
A₈
A₉
Pin Configuration
SOJ
Top View
TSOP II
Top View
1
36 _NC
NC 1
44
2
35 _A18
NC 2
43
3
4
5
34 _A17
33 _A16
32 _A15
A₀ 3
A₁ 4
A₂ 5
A₃ 6
42
41
40
39
6
31 _OE
A₄ 7
38
7
30 _I/O7 CE 8
37
8
29 _I/O6 I/O0 9
36
9
10
11
28
27
26
GND
V_CC
I/O₅
I/O₁
V_CC
V_SS
I/O₂
10
11
12
13
35
34
33
32
12
25 I/O_{4 I/O3 14}
31
13
24 A₁₄
WE 15
30
14
15
16
23 A₁₃
22 A₁₂
21 _A11
A₅ 16
A₆ ¹⁷
A₇ 18
A₈ 19
29
28
27
26
17
20 A₁₀
A₉ 20
25
18
19 NC
NC 21
24
NC 22
23
NC
NC
NC
A₁₈
A₁₇
A₁₆
A₁₅
OE
I/O₇
I/O₆
V_SS
V_CC
I/O₅
I/O₄
A₁₄
A₁₃
A₁₂
A₁₁
A₁₀
NC
NC
NC
Selection Guide
-12
-15
-17
-20
-25
Maximum Access Time (ns)
12
15
17
20
25
Maximum Operating Current (mA) Comm’l
200
180
170
160
150
Ind’l
220
200
180
170
170
Maximum CMOS Standby
Com’l/Ind’l
8
8
8
8
8
Current (mA)
Com’l L
0.5
0.5
0.5
0.5
0.5
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05139 Rev. *A
Revised September 13, 2002