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CY7C1049BN_09 Datasheet, PDF (1/10 Pages) Cypress Semiconductor – 512K x 8 Static RAM
1CY7C1049BN
Features
• High speed
— tAA = 12 ns
• Low active power
— 1320 mW (max.)
• Low CMOS standby power (Commercial L version)
— 2.75 mW (max.)
• 2.0V Data Retention (400 µW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
Logic Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
CE
WE
OE
INPUT BUFFER
512K x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
CY7C1049BN
512K x 8 Static RAM
Functional Description[1]
The CY7C1049BN is a high-performance CMOS static RAM
organized as 524,288 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location
specified on the address pins (A0 through A18).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1049BN is available in a standard 400-mil-wide
36-pin SOJ package with center power and ground (revolu-
tionary) pinout.
Pin Configuration
SOJ
Top View
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
A0 1
A1 2
A2 3
A3 4
A4 5
CE 6
I/O0 7
I/O1 8
VCC 9
GND 10
I/O2 11
I/O3 12
WE 13
A5 14
A6 15
A7 16
A8 17
A9 18
36 NC
35 A18
34 A17
33 A16
32 A15
31 OE
30 I/O7
29 I/O6
28 GND
27 VCC
26 I/O5
25 I/O4
24 A14
23 A13
22 A12
21 A11
20 A10
19 NC
I/O6
I/O7
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-06501 Rev. **
Revised February 2, 2006