CY7C1049B Datasheet, PDF (1/10 Pages) Cypress Semiconductor – 512K x 8 Static RAM

049B
CY7C1049B
512K x 8 Static RAM
Features
• High speed
— t_AA = 12 ns
• Low active power
— 1320 mW (max.)
• Low CMOS standby power (Commercial L version)
— 2.75 mW (max.)
• 2.0V Data Retention (400 µW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
Functional Description^[1]
The CY7C1049B is a high-performance CMOS static RAM or-
ganized as 524,288 words by 8 bits. Easy memory expansion
Logic Block Diagram
is provided by an active LOW Chip Enable (CE), an active
LOW Output Enable (OE), and three-state drivers. Writing to
the device is accomplished by taking Chip Enable (CE) and
Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O₀
through I/O₇) is then written into the location specified on the
address pins (A₀ through A₁₈).
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O₀ through I/O₇) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1049B is available in a standard 400-mil-wide
36-pin SOJ package with center power and ground (revolu-
tionary) pinout.
Pin Configuration
SOJ
Top View
A₀
A₁
A₂
A₃
A₄
A₅
A₆
A₇
A₈
A₉
A₁₀
CE
WE
INPUT BUFFER
512K x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
I/O₀
I/O₁
I/O₂
I/O₃
I/O₄
I/O₅
I/O₆
I/O₇
A₀ 1
A_{1 2}
A₂ 3
A₃ 4
A_{4 5}
CE 6
I/O₀ 7
I/O₁ 8
V_CC 9
GND 10
I/O₂ 11
I/O3 12
WE 13
A₅ 14
A₆ 15
A₇ 16
A_{8 17}
A_{9 18}
36 NC
35 A₁₈
34 A₁₇
33 A₁₆
32 A₁₅
31 OE
30 I/O₇
29 I/O₆
28 _GND
27 _VCC
26 I/O₅
25 I/O₄
24 A₁₄
23 A₁₃
22 A₁₂
21 A₁₁
20 A₁₀
19 NC
OE
Selection Guide
7C1049B-12 7C1049B-15 7C1049B-17 7C1049B-20 7C1049B-25
Maximum Access Time (ns)
12
15
17
20
25
Maximum Operating Current (mA)
240
220
195
185
180
Maximum CMOS Standby
Current (mA)
Com’l
8
Com’l/Ind’l L
-
8
8
8
8
-
0.5
0.5
0.5
Ind’l
-
-
-
9
9
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05169 Rev. *A
Revised September 13, 2002