CY7C1046DV33_10 Datasheet, PDF (1/14 Pages) Cypress Semiconductor – 4-Mbit (1 M × 4) Static RAM

CY7C1046DV33
4-Mbit (1 M × 4) Static RAM
4-Mbit (1 M × 4) Static RAM
Features
■ Pin- and function-compatible with CY7C1046CV33
■ High speed
❐ t_AA = 10 ns
■ Low active power
❐ I_CC = 90 mA @ 10 ns
■ Low CMOS standby power
❐ I_SB2 = 10 mA
■ 2.0 V data retention
■ Automatic power-down when deselected
■ TTL-compatible inputs and outputs
■ Easy memory expansion with CE and OE features
■ Available in lead-free 400-mil-wide 32-pin SOJ package
Logic Block Diagram
Functional Description
The CY7C1046DV33^[1] is a high-performance CMOS static
RAM organized as 1M words by 4 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and tri-state drivers. Writing
to the device is accomplished by taking Chip Enable (CE) and
Write Enable (WE) inputs LOW. Data on the four I/O pins (I/O₀
through I/O₃) is then written into the location specified on the
address pins (A₀ through A₁₉).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The four input/output pins (I/O₀ through I/O₃) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a Write
operation (CE LOW, and WE LOW).
The CY7C1046DV33 is available in a standard 400-mil-wide
32-pin SOJ package with center power and ground
(revolutionary) pinout.
A₀
A₁
A₂
AA₃₄
AA₅₆
AA₇₈
A₉
A₁₀
CE
WE
OE
INPUT BUFFER
1 Mbit x 4
COLUMN
DECODER
POWER
DOWN
I/O₀
I/O₁
I/O₂
I/O₃
Note
1. For guidelines on SRAM system design, please refer to the System Design Guidelines Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05611 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 2, 2010
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