CY7C1046D Datasheet, PDF (1/8 Pages) Cypress Semiconductor – 4-Mbit (1M x 4) Static RAM

CY7C1046D
Features
• Pin- and function-compatible with CY7C1046B
• High speed
— t_AA = 10 ns
• CMOS for optimum speed/power
• Low active power
— I_CC = 90 mA @ 10 ns
• Low CMOS Standby Power
— I_SB2 = 10 mA
• Data Retention at 2.0 V
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
• Available in lead-free 400-mil-wide 32-pin SOJ package
Logic Block Diagram
4-Mbit (1M x 4) Static RAM
Functional Description^[1]
The CY7C1046D is a high-performance CMOS static RAM
organized as 1M words by 4 bits. Easy memory expansion is
provided by an active LOW Chip Enable (CE), an active LOW
Output Enable (OE), and tri-state drivers. Writing to the device
is accomplished by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. Data on the four I/O pins (I/O₀ through I/O₃)
is then written into the location specified on the address pins
(A₀ through A₁₉).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The four input/output pins (I/O₀ through I/O₃) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1046D is available in a standard 400-mil-wide
32-pin SOJ package with center power and ground (revolu-
tionary) pinout.
Pin Configuration
SOJ
Top View
A₀
A₁
A₂
A₃
A₄
A₅
A₆
A₇
A₈
A₉
A₁₀
CE
WE
INPUT BUFFER
1M x 4
COLUMN
DECODER
POWER
DOWN
A₀ 1
A_{1 2}
A₂ 3
A₃ 4
A_{4 5}
CE ₆
32 _A19
31 A₁₈
30 _A17
29 _A16
28 A₁₅
27 _OE
I/O₀
I/O_{0 7}
V_CC 8
26 I/O₃
25 _GND
I/O₁
GND 9
I/O₁ 10
24 _VCC
23 I/O₂
I/O₂
WE 11
A_{5 12}
22 A₁₄
21 A₁₃
I/O₃
A_{6 13}
A_{7 14}
20 A₁₂
19 A₁₁
A_{8 15}
18 A₁₀
A_{9 16}
17 NC
OE
Selection Guide
-10
Unit
Maximum Access Time
10
ns
Maximum Operating Current
90
mA
Maximum CMOS Standby Current (mA)
10
mA
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05705 Rev. *B
Revised April 3, 2006
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