CY7C1041DV33_11 Datasheet, PDF (1/17 Pages) Cypress Semiconductor – 4-Mbit (256 K × 16) Static RAM

CY7C1041DV33
4-Mbit (256 K × 16) Static RAM
4-Mbit (256 K × 16) Static RAM
Features
■ Temperature ranges
❐ Industrial: –40 °C to 85 °C
❐ Automotive-A ^[1] : –40 °C to 85 °C
❐ Automotive-E ^[1] : –40 °C to 125 °C
■ Pin and function compatible with CY7C1041CV33
■ High speed
❐ t_AA = 10 ns
■ Low active power
❐ I_CC = 90 mA at 10 ns (industrial)
■ Low CMOS standby power
❐ I_SB2 = 10 mA
■ 2.0 V data retention
■ Automatic power-down when deselected
■ TTL compatible inputs and outputs
■ Easy memory expansion with CE and OE features
■ Available in Pb-free 48-ball VFBGA, 44-pin (400-mil) molded
SOJ, and 44-pin TSOP II Packages
Logic Block Diagram
Functional Description
The CY7C1041DV33 is a high performance CMOS Static RAM
organized as 256 K words by 16-bits. To write to the device, take
chip enable (CE) and write enable (WE) inputs LOW. If byte low
enable (BLE) is LOW, then data from I/O pins (I/O₀ to I/O₇) is
written into the location specified on the address pins (A₀ to A₁₇).
If byte high enable (BHE) is LOW, then data from I/O pins (I/O₈
to I/O₁₅) is written into the location specified on the address pins
(A₀ to A₁₇).
To read from the device, take chip enable (CE) and output enable
(OE) LOW while forcing the write enable (WE) HIGH. If BLE is
LOW, then data from the memory location specified by the
address pins appears on I/O₀ to I/O₇. If BHE is LOW, then data
from memory appears on I/O₈ to I/O₁₅. See the Truth Table on
page 10 for a complete description of read and write modes.
The input and output pins (I/O₀ to I/O₁₅) are placed in a high
impedance state when the device is deselected (CE HIGH),
outputs are disabled (OE HIGH), BHE and BLE are disabled
(BHE, BLE HIGH), or during a write operation (CE LOW and WE
LOW).
The CY7C1041DV33 is available in a standard 44-pin 400-mil
wide SOJ and 44-pin TSOP II package with center power and
ground (revolutionary) pinout and a 48-ball fine-pitch ball grid
array (FBGA) package.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
INPUT BUFFER
A₀
A₁
A₂
A₃
A₄
256K × 16
A₅
A₆
A₇
A₈
IO₀–IO₇
IO₈–IO₁₅
COLUMN
DECODER
BHE
WE
CE
OE
BLE
Note
1. Automotive product information is preliminary.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05473 Rev. *I
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 24, 2011
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