CY7C1041DV33 Datasheet, PDF (1/14 Pages) Cypress Semiconductor – 4-Mbit (256K x 16) Static RAM

CY7C1041DV33
4-Mbit (256K x 16) Static RAM
Features
• Pin- and function-compatible with CY7C1041CV33
• High speed
— t_AA =10 ns
• Low active power
— I_CC = 90 mA @ 10 ns (Industrial)
• Low CMOS standby power
— I_SB2 = 10 mA
• 2.0 V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
• Available in lead-free 48-ball VFBGA, 44-lead (400-mil)
Molded SOJ and 44-pin TSOP II packages
Logic Block Diagram
A₀
A₁
A₂
A₃
A₄
A₅
A₆
A₇
A₈
INPUT BUFFER
256K × 16
COLUMN
DECODER
Functional Description^[1]
The CY7C1041DV33 is a high-performance CMOS Static
RAM organized as 256K words by 16 bits. Writing to the device
is accomplished by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte LOW Enable (BLE) is LOW, then
data from I/O pins (I/O₀–I/O₇), is written into the location
specified on the address pins (A₀–A₁₇). If Byte HIGH Enable
(BHE) is LOW, then data from I/O pins (I/O₈–I/O₁₅) is written
into the location specified on the address pins (A₀–A₁₇).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte LOW Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O₀ – I/O₇. If Byte HIGH Enable (BHE) is
LOW, then data from memory will appear on I/O₈ to I/O₁₅. See
the truth table at the back of this data sheet for a complete
description of Read and Write modes.
The input/output pins (I/O₀–I/O₁₅) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a Write operation
(CE LOW, and WE LOW).
The CY7C1041DV33 is available in a standard 44-pin
400-mil-wide body width SOJ and 44-pin TSOP II package
with center power and ground (revolutionary) pinout, as well
as a 48-ball fine-pitch ball grid array (FBGA) package.
I/O₀–I/O₇
I/O₈–I/O₁₅
BHE
WE
CE
OE
BLE
Note
1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05473 Rev. *D
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised July 17, 2006
[+] Feedback