CY7C1041D Datasheet, PDF(1/9 Page) Cypress Semiconductor

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CY7C1041D Datasheet, PDF (1/9 Pages) Cypress Semiconductor – 4-Mbit (256K x 16) Static RAM

CY7C1041D

4-Mbit (256K x 16) Static RAM

Features

â¢ Pin-and function-compatible with CY7C1041B

â¢ High speed

â tAA = 10 ns

â¢ Low active power

â ICC = 90 mA @ 10 ns (Industrial)

â¢ Low CMOS standby power

â ISB2 = 10 mA

â¢ 2.0 V Data Retention

â¢ Automatic power-down when deselected

â¢ TTL-compatible inputs and outputs

â¢ Easy memory expansion with CE and OE features

â¢ Available in lead-free 44-Lead (400-Mil) Molded SOJ and

44-Pin TSOP II packages

Logic Block Diagram

Functional Description[1]

The CY7C1041D is a high-performance CMOS static RAM

organized as 256K words by 16 bits. Writing to the device is

accomplished by taking Chip Enable (CE) and Write Enable

(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data

from I/O pins (I/O0 through I/O7), is written into the location

specified on the address pins (A0 through A17). If Byte High

Enable (BHE) is LOW, then data from I/O pins (I/O8 through

I/O15) is written into the location specified on the address pins

(A0 through A17).

Reading from the device is accomplished by taking Chip

Enable (CE) and Output Enable (OE) LOW while forcing the

Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,

then data from the memory location specified by the address

pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is

LOW, then data from memory will appear on I/O8 to I/O15. See

the truth table at the back of this data sheet for a complete

description of read and write modes.

The input/output pins (I/O0 through I/O15) are placed in a

high-impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), the BHE and BLE

are disabled (BHE, BLE HIGH), or during a write operation (CE

LOW, and WE LOW).

The CY7C1041D is available in a standard 44-pin

400-mil-wide body width SOJ and 44-pin TSOP II package

with center power and ground (revolutionary) pinout.

Pin Configurations

INPUT BUFFER

256K x 16

COLUMN

DECODER

I/O0âI/O7

I/O8âI/O15

BHE

BLE

SOJ / TSOPII

Top View

A0 1

A1 2

A2 3

A3 4

A4 5

CE 6

I/O0 7

I/O1 8

I/O2 9

I/O3 10

VCC 11

VSS 12

I/O4 13

I/O5 14

I/O6 15

I/O7 16

WE 17

A5 18

A6 19

A7 20

A8 21

A9 22

44 A17

43 A16

42 A15

41 OE

40 BHE

39 BLE

38 I/O15

37 I/O14

36 I/O13

35 I/O12

34 VSS

33 VCC

32 I/O11

31 I/O10

30 I/O9

29 I/O8

28 NC

27 A14

26 A13

25 A12

24 A11

23 A10

Note:

1. For guidelines on SRAM system design, please refer to the âSystem Design Guidelinesâ Cypress application note, available on the internet at www.cypress.com.

Cypress Semiconductor Corporation â¢ 198 Champion Court â¢ San Jose, CA 95134-1709 â¢ 408-943-2600

Document #: 38-05472 Rev. *C

Revised March 31, 2006

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