CY7C1041CV33_06 Datasheet, PDF (1/12 Pages) Cypress Semiconductor – 4-Mbit (256K x 16) Static RAM

CY7C1041CV33
4-Mbit (256K x 16) Static RAM
Features
• Pin equivalent to CY7C1041BV33
• Temperature Ranges
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive-A: –40°C to 85°C
— Automotive-E: –40°C to 125°C
• High speed
— t_AA = 10 ns
• Low active power
— 324 mW (max.)
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
• Available in Pb-free and non Pb-free 44-pin 400-mil-
SOJ, 44-pin TSOP II and 48-ball FBGA packages
Functional Description^[1]
The CY7C1041CV33 is a high-performance CMOS Static
RAM organized as 262,144 words by 16 bits.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte LOW Enable
(BLE) is LOW, then data from I/O pins (I/O₀–I/O₇), is written
into the location specified on the address pins (A₀–A₁₇). If Byte
HIGH Enable (BHE) is LOW, then data from I/O pins
(I/O₈–I/O₁₅) is written into the location specified on the
address pins (A₀–A₁₇).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte LOW Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O₀ – I/O₇. If Byte HIGH Enable (BHE) is
LOW, then data from memory will appear on I/O₈ to I/O₁₅. See
the truth table at the back of this data sheet for a complete
description of Read and Write modes.
The input/output pins (I/O₀–I/O₁₅) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a Write operation
(CE LOW, and WE LOW).
The CY7C1041CV33 is available in a standard 44-pin
400-mil-wide body width SOJ and 44-pin TSOP II package
with center power and ground (revolutionary) pinout, as well
as a 48-ball fine-pitch ball grid array (FBGA) package.
Logic Block Diagram
INPUT BUFFER
Pin Configuration
SOJ/
TSOP II
Top View
A₀
A₁
A₂
A₃
256K × 16
A₄
ARRAY
A₅
A₆
A₇
A₈
COLUMN
DECODER
I/O₀–I/O₇
I/O₈–I/O₁₅
BHE
WE
CE
OE
BLE
A₀ 1
A₁ 2
A₂ 3
A₃ 4
A₄ 5
CE 6
I/O₀ 7
I/O₁ 8
I/O₂ 9
I/O₃ 10
V_CC 11
V_SS 12
I/O₄ 13
I/O₅ 14
I/O₆ 15
I/O₇ 16
WE 17
A₅ ¹⁸
A₆ 19
A₇ 20
A₈ 21
A₉ 22
44 _A17
43 A₁₆
42 _A15
41 _OE
40 _BHE
39 _BLE
38 _I/O15
37 _I/O14
36 _I/O13
35 _I/O12
34 _VSS
33 _VCC
32 I/O₁₁
31 I/O₁₀
30 I/O₉
29 I/O₈
28 _NC
27 _A14
26 A₁₃
25 A₁₂
24 A11
23 A₁₀
Notes:
1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05134 Rev. *H
Revised September 1, 2006
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