CY7C1041B Datasheet, PDF(1/10 Page) Cypress Semiconductor

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CY7C1041B Datasheet, PDF (1/10 Pages) Cypress Semiconductor – 256K x 16 Static RAM

1CY7C1041B

CY7C1041B

256K x 16 Static RAM

Features

â¢ High speed

â tAA = 12 ns

â¢ Low active power

â 1540 mW (max.)

â¢ Low CMOS standby power (L version)

â 2.75 mW (max.)

â¢ 2.0V Data Retention (400 ÂµW at 2.0V retention)

â¢ Automatic power-down when deselected

â¢ TTL-compatible inputs and outputs

â¢ Easy memory expansion with CE and OE features

Functional Description

The CY7C1041B is a high-performance CMOS static RAM or-

ganized as 262,144 words by 16 bits.

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable

(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is

Logic Block Diagram

written into the location specified on the address pins (A0

through A17). If Byte High Enable (BHE) is LOW, then data

from I/O pins (I/O8 through I/O15) is written into the location

specified on the address pins (A0 through A17).

Reading from the device is accomplished by taking Chip En-

able (CE) and Output Enable (OE) LOW while forcing the Write

Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then

data from the memory location specified by the address pins

will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW,

then data from memory will appear on I/O8 to I/O15. See the

truth table at the back of this data sheet for a complete descrip-

tion of read and write modes.

The input/output pins (I/O0 through I/O15) are placed in a

high-impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), the BHE and BLE

are disabled (BHE, BLE HIGH), or during a write operation (CE

LOW, and WE LOW).

The CY7C1041B is available in a standard 44-pin

400-mil-wide body width SOJ and 44-pin TSOP II package

with center power and ground (revolutionary) pinout.

Pin Configuration

INPUT BUFFER

256K x 16

ARRAY

1024 x 4096

COLUMN

DECODER

Selection Guide

Maximum Access Time (ns)

Maximum Operating Current (mA) Comâl

Indâl

Maximum CMOS Standby Current Comâl

(mA)

Comâl

Indâl

I/O0 â I/O7

I/O8 â I/O15

BHE

BLE

1041Bâ1

7C1041B-12

200

220

7C1041B-15

190

210

0.5

SOJ

TSOP II

Top View

A0 1

A1 2

A2 3

A3 4

A4 5

CE 6

I/O0 7

I/O1 8

I/O2 9

I/O3 10

VCC 11

VSS 12

I/O4 13

I/O5 14

I/O6 15

I/O7 16

WE 17

A5 18

A6 19

A7 20

A8 21

A9 22

A17

A16

A15

BHE

BLE

I/O15

I/O14

I/O13

I/O12

VSS

VCC

I/O11

I/O10

I/O9

I/O8

A14

A13

A12

A11

A10

1041Bâ2

7C1041B-17

180

200

0.5

7C1041B-20

170

190

0.5

7C1041B-25

160

180

0.5

Cypress Semiconductor Corporation â¢ 3901 North First Street â¢ San Jose â¢ CA 95134 â¢ 408-943-2600

March 23, 2001

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