CY7C1034DV33 Datasheet, PDF (1/8 Pages) Cypress Semiconductor – 6-Mbit (256K X 24) Static RAM

PRELIMINARY
CY7C1034DV33
6-Mbit (256K X 24) Static RAM
Features
• High speed
— t_AA = 8 ns
• Low active power
— I_CC = 185 mA @ 8 ns
• Low CMOS standby power
— I_SB2 = 25 mA
• Operating voltages of 3.3 ± 0.3V
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE₁, CE₂ and CE₃
features
• Available in Pb-Free Standard 119-ball PBGA
Functional Block Diagram
A₀
A₁
A₂
A₃
A₄
A₅
A₆
A₇
A₈
A₉
INPUT BUFFER
256K x 24
ARRAY
COLUMN
DECODER
Functional Description
The CY7C1034DV33 is a high-performance CMOS static
RAM organized as 256K words by 24 bits. This device has an
automatic power-down feature that significantly reduces
power consumption when deselected.
To write to the device, enable the chip (CE₁ LOW, CE₂ HIGH
and CE₃ LOW) while forcing the Write Enable (WE) input
LOW.
To read from the device, enable the chip by taking CE₁ LOW
CE₂ HIGH and CE₃ LOW while forcing the Output Enable (OE)
LOW and the Write Enable (WE) HIGH. See the truth table at
the back of this data sheet for a complete description of Read
and Write modes.
The 24 I/O pins (I/O₀–I/O₂₃) are placed in a high-impedance
state when the device is deselected (CE₁ HIGH/CE₂
LOW/CE₃ HIGH) or when the output enable (OE) is HIGH
during a Write operation. (CE₁ LOW, CE₂ HIGH, CE₃ LOW
and WE LOW).
I/O₀–I/O₂₃
CONTROL LOGIC
CE₁, CE₂, CE₃
WE
OE
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
–8
Unit
8
ns
185
mA
25
mA
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-08351 Rev. *A
Revised September 4, 2006
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