CY7C1031 Datasheet, PDF (1/13 Pages) Cypress Semiconductor – 64K x 18 Synchronous Cache RAM

CY7C1031
CY7C1032
64K x 18 Synchronous Cache RAM
Features
Functional Description
• Supports 66-MHz Pentium^® microprocessor cache
systems with zero wait states
• 64K by 18 common I/O
• Fast clock-to-output times
— 8.5 ns
• Two-bit wraparound counter supporting Pentium
microprocessor and 486 burst sequence (CY7C1031)
• Two-bit wraparound counter supporting linear burst
sequence (CY7C1032)
• Separate processor and controller address strobes
• Synchronous self-timed write
• Direct interface with the processor and external cache
controller
• Asynchronous output enable
• I/Os capable of 3.3V operation
• JEDEC-standard pinout
• 52-pin PLCC packaging
The CY7C1031 and CY7C1032 are 64K by 18 synchronous
cache RAMs designed to interface with high-speed micropro-
cessors with minimum glue logic. Maximum access delay from
clock rise is 8.5 ns. A 2-bit on-chip counter captures the first
address in a burst and increments the address automatically
for the rest of the burst access.
The CY7C1031 is designed for Intel^® Pentium and i486
CPU-based systems; its counter follows the burst sequence of
the Pentium and the i486 processors. The CY7C1032 is archi-
tected for processors with linear burst sequences. Burst
accesses can be initiated with the processor address strobe
(ADSP) or the cache controller address strobe (ADSC) inputs.
Address advancement is controlled by the address
advancement (ADV) input.
A synchronous self-timed write mechanism is provided to
simplify the write interface. A synchronous chip select input
and an asynchronous output enable input provide easy control
for bank selection and output three-state control.
Logic Block Diagram
18
Pin Configuration
PLCC
Top View
A₁₅ –A₀
ADV
16 14
ADDR
REG ₁₄
2
2
ADV
LOGIC
DATA _IN
REGISTER
9
9
16
64K X 9
64K X 9
RAM ARRAY RAM ARRAY
CLK
ADSP
ADSC
CS
WH
WL
WH
TIMING
WL
CONTROL
9
9
DQ₈
DQ₉
V_CCQ
V_SSQ
DQ₁₀
DQ₁₁
DQ₁₂
DQ₁₃
V_SSQ
V_CCQ
DQ₁₄
DDPQ₁^[115]
7 6 5 4 3 2 1 52 51 50 49 48 47
8
46
9
45
10
44
11
43
12
42
13
7C1031
41
14
7C1032
40
15
39
16
38
17
37
18
36
19
35
20
34
2122 23 24 25 26 27 28 29 30 31 32 33
[1]
DP₀
DQ₇
DQ₆
V_CCQ
V_SSQ
DQ₅
DQ₄
DQ₃
DQ₂
V_SSQ
V_CCQ
DQ₁
DQ₀
18
OE
Selection Guide
Maximum Access Time
Maximum Operating Current
Commercial
Note:
1. DP₀ and DP₁ are functionally equivalent to DQ_x.
DQ₁₅ – DQ₀
DP₁– DP₀
7C1031-8
7C1032-8
8.5
280
7C1031-10
7C1032-10
10
280
7C1031-12
Unit
12
ns
230
mA
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05278 Rev. *A
Revised April 1, 2004