CY7C1024DV33_07 Datasheet, PDF (1/9 Pages) Cypress Semiconductor – 3-Mbit (128K X 24) Static RAM

CY7C1024DV33
3-Mbit (128K X 24) Static RAM
Features
■ High speed
❐ t_AA = 8 ns
■ Low active power
❐ I_CC = 225 mA at 8 ns
■ Low CMOS standby power
❐ I_SB2 = 25 mA
■ Operating voltages of 3.3 ± 0.3V
■ 2.0V data retention
■ Automatic power down when deselected
■ TTL compatible inputs and outputs
■ Easy memory expansion with CE₁, CE₂, and CE₃ features
■ Available in Pb-free standard 119-Ball PBGA
Functional Description
The CY7C1024DV33 is a high performance CMOS static RAM
organized as 128K words by 24 bits. This device has an
automatic power down feature that significantly reduces power
consumption when deselected.
To write to the device, enable the chip (CE₁ LOW, CE₂ HIGH,
and CE₃ LOW), while forcing the Write Enable (WE) input LOW.
To read from the device, enable the chip by taking CE₁ LOW, CE₂
HIGH, and CE₃ LOW while forcing the Output Enable (OE) LOW
and the Write Enable (WE) HIGH. See the Truth Table on page
7 for a complete description of Read and Write modes.
The 24 IO pins (IO₀ – IO₂₃) are placed in a high impedance state
when the device is deselected (CE₁ HIGH, CE₂ LOW, or CE₃
HIGH) or when the output enable (OE) is HIGH during a write
operation. (CE₁ LOW, CE₂ HIGH, CE₃ LOW, and WE LOW).
Logic Block Diagram
A_(9:0)
INPUT BUFFER
128K x 24
ARRAY
IO₀ – IO₂₃
COLUMN
DECODER
A_(16:10)
CONTROL LOGIC
CE₁, CE₂, CE₃
WE
OE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-08353 Rev. *B
• San Jose, CA 95134-1709 • 408-943-2600
Revised September10, 2007