CY7C1021CV33_06 Datasheet, PDF (1/13 Pages) Cypress Semiconductor – 1-Mbit (64K x 16) Static RAM

CY7C1021CV33
1-Mbit (64K x 16) Static RAM
Features
• Temperature Ranges
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive-A: –40°C to 85°C
— Automotive-E: –40°C to 125°C
• Pin- and function-compatible with CY7C1021BV33
• High speed
— t_AA = 8 ns (Commercial & Industrial)
— t_AA = 12 ns (Automotive)
• CMOS for optimum speed/power
• Low active power: 345 mW (max.)
• Automatic power-down when deselected
• Independent control of upper and lower bits
• Available in Pb-free and non Pb-free 44-pin 400-Mil SOJ
44-pin TSOP II and 48-ball FBGA packages
Functional Description^[1]
The CY7C1021CV33 is a high-performance CMOS static
RAM organized as 65,536 words by 16 bits. This device has
an automatic power-down feature that significantly reduces
power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O₁ through I/O₈), is
written into the location specified on the address pins (A₀
through A₁₅). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O₉ through I/O₁₆) is written into the location
specified on the address pins (A₀ through A₁₅).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O₁ to I/O₈. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O₉ to I/O₁₆. See
the truth table at the end of this data sheet for a complete
description of Read and Write modes.
The input/output pins (I/O₁ through I/O₁₆) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a Write operation
(CE LOW, and WE LOW).
The CY7C1021CV33 is available in 44-pin 400-Mil wide SOJ,
44-pin TSOP II and 48-ball FBGA packages.
Logic Block Diagram
DATA IN DRIVERS
A₇
A₆
A₅
A₄
64K x 16
A₃
RAM Array
A₂
A₁
A₀
I/O₁–I/O₈
I/O₉–I/O₁₆
COLUMN DECODER
BHE
WE
CE
OE
BLE
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05132 Rev. *G
Revised November 6, 2006
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