CY7C1021CV33 Datasheet, PDF (1/12 Pages) Cypress Semiconductor – 64K x 16 Static RAM

CY7C1021CV33
64K x 16 Static RAM
Features
• Pin- and function-compatible with CY7C1021BV33
• High speed
— t_AA = 8, 10, 12, and 15 ns
• CMOS for optimum speed/power
• Low active power
— 360 mW (max.)
• Data retention at 2.0V
• Automatic power-down when deselected
• Independent control of upper and lower bits
• Available in 44-pin TSOP II, 400-mil SOJ, 48-ball FBGA
Functional Description
The CY7C1021CV33 is a high-performance CMOS static
RAM organized as 65,536 words by 16 bits. This device has
an automatic power-down feature that significantly reduces
power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
Logic Block Diagram
DATA IN DRIVERS
A₇
A₆
A₅
64K x 16
A₄
RAM Array
A₃
512 X 2048
A₂
A₁
A₀
COLUMN DECODER
(BLE) is LOW, then data from I/O pins (I/O₁ through I/O₈), is
written into the location specified on the address pins (A₀
through A₁₅). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O₉ through I/O₁₆) is written into the location
specified on the address pins (A₀ through A₁₅).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O₁ to I/O₈. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O₉ to I/O₁₆. See
the truth table at the end of this data sheet for a complete
description of Read and Write modes.
The input/output pins (I/O₁ through I/O₁₆) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a Write operation
(CE LOW, and WE LOW).
The CY7C1021CV33 is available in standard 44-pin TSOP
Type II 400-mil-wide SOJ packages, as well as a 48-ball
FBGA.
I/O₁–I/O₈
I/O₉–I/O₁₆
BHE
WE
CE
OE
BLE
Pin Configuration
SOJ / TSOP II
Top View
A₄ 1
A₃ 2
A₂ 3
A₁ 4
A₀ 5
CE 6
I/O₁ 7
I/O₂ 8
I/O₃ 9
I/O₄ 10
V_CC 11
V_SS 12
I/O₅ 13
I/O₆ 14
I/O₇ 15
I/O₈ 16
WE 17
A₁₅ ¹⁸
A₁₄ 19
A₁₃ 20
A₁₂ 21
NC 22
44 _A5
43 A₆
42 _A7
41 OE
40 _BHE
39 _BLE
38 _I/O16
37 _I/O15
36 _I/O14
35 _I/O13
34 _VSS
33 _VCC
32 I/O₁₂
31 I/O₁₁
30 I/O₁₀
29 I/O₉
28 _NC
27 A₈
26 A₉
25 A₁₀
24 A11
23 NC
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
CY7C1021CV33-8
8
95
5
CY7C1021CV33-10 CY7C1021CV33-12 CY7C1021CV33-15 Unit
10
12
15
ns
90
85
80
mA
5
5
5
mA
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05132 Rev. *C
Revised October 30, 2002